\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Active size register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VASZ : Size of the vertical active area width plus back porch and synchronous pulse
bits : 0 - 11 (12 bit)
HASZ : Size of the horizontal active area width plus back porch and synchronous pulse
bits : 16 - 27 (12 bit)
Layer 1 control register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEN : Layer enable
bits : 0 - 0 (1 bit)
CKEYEN : Color keying enable
bits : 1 - 1 (1 bit)
LUTEN : LUT enable
bits : 4 - 4 (1 bit)
Layer 1 horizontal position parameters register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WLP : Window left position
bits : 0 - 11 (12 bit)
WRP : Window right position
bits : 16 - 27 (12 bit)
Layer 1 vertical position parameters register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WTP : Window top position
bits : 0 - 11 (12 bit)
WBP : Window bottom position
bits : 16 - 27 (12 bit)
Layer 1 color key register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKEYB : Color Key Blue
bits : 0 - 7 (8 bit)
CKEYG : Color Key Green
bits : 8 - 15 (8 bit)
CKEYR : Color Key Red
bits : 16 - 23 (8 bit)
Layer 1 packeted pixel format register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPF : Packeted Pixel Format
bits : 0 - 2 (3 bit)
Layer 1 specified alpha register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Specified alpha
bits : 0 - 7 (8 bit)
Layer 1 default color register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCB : The default color blue
bits : 0 - 7 (8 bit)
DCG : The default color green
bits : 8 - 15 (8 bit)
DCR : The default color red
bits : 16 - 23 (8 bit)
DCA : The default color ALPHA
bits : 24 - 31 (8 bit)
Layer 1 blending register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACF2 : Alpha Calculation Factor 2 of Blending Method
bits : 0 - 2 (3 bit)
ACF1 : Alpha Calculation Factor 1 of Blending Method
bits : 8 - 10 (3 bit)
Layer 1 frame base address register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBADD : Frame Buffer base Address
bits : 0 - 31 (32 bit)
Layer 1 frame line length register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLL : Frame Line Length
bits : 0 - 13 (14 bit)
STDOFF : Frame Buffer Stride Offset
bits : 16 - 29 (14 bit)
Layer 1 frame total line number register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTLN : Frame Total Line Number
bits : 0 - 10 (11 bit)
Total size register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTSZ : Vertical total size of the display
bits : 0 - 11 (12 bit)
HTSZ : Horizontal total size of the display
bits : 16 - 27 (12 bit)
Layer 1 look up table register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TB : Blue channel of a LUT entry
bits : 0 - 7 (8 bit)
TG : Green channel of a LUT entry
bits : 8 - 15 (8 bit)
TR : Red channel of a LUT entry
bits : 16 - 23 (8 bit)
TADD : Look Up Table Write Address
bits : 24 - 31 (8 bit)
Control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLIEN : TLI enable bit
bits : 0 - 0 (1 bit)
BDB : Blue channel Dither Bits Number
bits : 4 - 6 (3 bit)
GDB : Green channel Dither Bits Number
bits : 8 - 10 (3 bit)
RDB : Red channel Dither Bits Number
bits : 12 - 14 (3 bit)
DFEN : Dither Function Enable
bits : 16 - 16 (1 bit)
CLKPS : Pixel Clock Polarity Selection
bits : 28 - 28 (1 bit)
DEPS : Data Enable Polarity Selection
bits : 29 - 29 (1 bit)
VPPS : Vertical Pulse Polarity Selection
bits : 30 - 30 (1 bit)
HPPS : Horizontal Pulse Polarity Selection
bits : 31 - 31 (1 bit)
Reload layer register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RQR : Request Reload
bits : 0 - 0 (1 bit)
FBR : Frame Blank Reload
bits : 1 - 1 (1 bit)
Background color register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BVB : Background value blue
bits : 0 - 7 (8 bit)
BVG : Background value green
bits : 8 - 15 (8 bit)
BVR : Background value red
bits : 16 - 23 (8 bit)
Interrupt enable register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LMIE : Line Mark Interrupt Enable
bits : 0 - 0 (1 bit)
FEIE : FIFO Error Interrupt Enable
bits : 1 - 1 (1 bit)
TEIE : Transaction Error Interrupt Enable
bits : 2 - 2 (1 bit)
LCRIE : Layer Configuration Reloaded Interrupt Enable
bits : 3 - 3 (1 bit)
Interrupt flag register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LMF : Line Mark Flag
bits : 0 - 0 (1 bit)
FEF : FIFO Error Flag
bits : 1 - 1 (1 bit)
TEF : Transaction Error Flag
bits : 2 - 2 (1 bit)
LCRF : Layer Configuration Reloaded Flag
bits : 3 - 3 (1 bit)
Interrupt flag clear register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LMC : Line Mark Flag Clear
bits : 0 - 0 (1 bit)
FEC : FIFO Error Flag Clear
bits : 1 - 1 (1 bit)
TEC : Transaction Error Flag Clear
bits : 2 - 2 (1 bit)
LCRC : Layer Configuration Reloaded Flag Clear
bits : 3 - 3 (1 bit)
Line mark register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LM : Line Mark value
bits : 0 - 10 (11 bit)
Current pixel position register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VPOS : Vertical position
bits : 0 - 15 (16 bit)
HPOS : Horizontal position
bits : 16 - 31 (16 bit)
Status register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VDE : Current VDE status
bits : 0 - 0 (1 bit)
HDE : Current HDE status
bits : 1 - 1 (1 bit)
VS : Current VS staus of the TLI
bits : 2 - 2 (1 bit)
HS : Current HS staus of the TLI
bits : 3 - 3 (1 bit)
Synchronous pulse size register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VPSZ : size of vertical synchronous pluse
bits : 0 - 11 (12 bit)
HPSZ : size of horizontal synchronous pluse
bits : 16 - 27 (12 bit)
Layer 0 control register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEN : Layer enable
bits : 0 - 0 (1 bit)
CKEYEN : Color keying enable
bits : 1 - 1 (1 bit)
LUTEN : LUT enable
bits : 4 - 4 (1 bit)
Layer 0 horizontal position parameters register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WLP : Window left position
bits : 0 - 11 (12 bit)
WRP : Window right position
bits : 16 - 27 (12 bit)
Layer 0 vertical position parameters register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WTP : Window top position
bits : 0 - 11 (12 bit)
WBP : Window bottom position
bits : 16 - 27 (12 bit)
Layer 0 color key register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKEYB : Color Key Blue
bits : 0 - 7 (8 bit)
CKEYG : Color Key Green
bits : 8 - 15 (8 bit)
CKEYR : Color Key Red
bits : 16 - 23 (8 bit)
Layer 0 packeted pixel format register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPF : Packeted Pixel Format
bits : 0 - 2 (3 bit)
Layer 0 specified alpha register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Specified alpha
bits : 0 - 7 (8 bit)
Layer 0 default color register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCB : The default color blue
bits : 0 - 7 (8 bit)
DCG : The default color green
bits : 8 - 15 (8 bit)
DCR : The default color red
bits : 16 - 23 (8 bit)
DCA : The default color ALPHA
bits : 24 - 31 (8 bit)
Layer 0 blending register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACF2 : Alpha Calculation Factor 2 of Blending Method
bits : 0 - 2 (3 bit)
ACF1 : Alpha Calculation Factor 1 of Blending Method
bits : 8 - 10 (3 bit)
Layer 0 frame base address register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBADD : Frame Buffer base Address
bits : 0 - 31 (32 bit)
Layer 0 frame line length register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLL : Frame Line Length
bits : 0 - 13 (14 bit)
STDOFF : Frame Buffer Stride Offset
bits : 16 - 29 (14 bit)
Layer 0 frame total line number register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTLN : Frame Total Line Number
bits : 0 - 10 (11 bit)
Back-porch size register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBPSZ : Size of the vertical back porch plus synchronous pulse
bits : 0 - 11 (12 bit)
HBPSZ : Size of the horizontal back porch plus synchronous pulse
bits : 16 - 27 (12 bit)
Layer 0 look up table register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TB : Blue channel of a LUT entry
bits : 0 - 7 (8 bit)
TG : Green channel of a LUT entry
bits : 8 - 15 (8 bit)
TR : Red Channel of a LUT entry
bits : 16 - 23 (8 bit)
TADD : Look Up Table Write Address
bits : 24 - 31 (8 bit)
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