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TLI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

ASZ

L1CTL

L1HPOS

L1VPOS

L1CKEY

L1PPF

L1SA

L1DC

L1BLEND

L1FBADDR

L1FLLEN

L1FTLN

TSZ

L1LUT

CLT (CTL)

RL

BGC

INTEN

INTF

INTC

LM

CPPOS

STAT

SPSZ

L0CTL

L0HPOS

L0VPOS

L0CKEY

L0PPF

L0SA

L0DC

L0BLEND

L0FBADDR

L0FLLEN

L0FTLN

BPSZ

L0LUT


ASZ

Active size register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASZ ASZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VASZ HASZ

VASZ : Size of the vertical active area width plus back porch and synchronous pulse
bits : 0 - 11 (12 bit)

HASZ : Size of the horizontal active area width plus back porch and synchronous pulse
bits : 16 - 27 (12 bit)


L1CTL

Layer 1 control register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1CTL L1CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEN CKEYEN LUTEN

LEN : Layer enable
bits : 0 - 0 (1 bit)

CKEYEN : Color keying enable
bits : 1 - 1 (1 bit)

LUTEN : LUT enable
bits : 4 - 4 (1 bit)


L1HPOS

Layer 1 horizontal position parameters register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1HPOS L1HPOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WLP WRP

WLP : Window left position
bits : 0 - 11 (12 bit)

WRP : Window right position
bits : 16 - 27 (12 bit)


L1VPOS

Layer 1 vertical position parameters register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1VPOS L1VPOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WTP WBP

WTP : Window top position
bits : 0 - 11 (12 bit)

WBP : Window bottom position
bits : 16 - 27 (12 bit)


L1CKEY

Layer 1 color key register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1CKEY L1CKEY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKEYB CKEYG CKEYR

CKEYB : Color Key Blue
bits : 0 - 7 (8 bit)

CKEYG : Color Key Green
bits : 8 - 15 (8 bit)

CKEYR : Color Key Red
bits : 16 - 23 (8 bit)


L1PPF

Layer 1 packeted pixel format register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1PPF L1PPF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPF

PPF : Packeted Pixel Format
bits : 0 - 2 (3 bit)


L1SA

Layer 1 specified alpha register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1SA L1SA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Specified alpha
bits : 0 - 7 (8 bit)


L1DC

Layer 1 default color register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1DC L1DC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCB DCG DCR DCA

DCB : The default color blue
bits : 0 - 7 (8 bit)

DCG : The default color green
bits : 8 - 15 (8 bit)

DCR : The default color red
bits : 16 - 23 (8 bit)

DCA : The default color ALPHA
bits : 24 - 31 (8 bit)


L1BLEND

Layer 1 blending register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1BLEND L1BLEND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACF2 ACF1

ACF2 : Alpha Calculation Factor 2 of Blending Method
bits : 0 - 2 (3 bit)

ACF1 : Alpha Calculation Factor 1 of Blending Method
bits : 8 - 10 (3 bit)


L1FBADDR

Layer 1 frame base address register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1FBADDR L1FBADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FBADD

FBADD : Frame Buffer base Address
bits : 0 - 31 (32 bit)


L1FLLEN

Layer 1 frame line length register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1FLLEN L1FLLEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLL STDOFF

FLL : Frame Line Length
bits : 0 - 13 (14 bit)

STDOFF : Frame Buffer Stride Offset
bits : 16 - 29 (14 bit)


L1FTLN

Layer 1 frame total line number register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1FTLN L1FTLN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTLN

FTLN : Frame Total Line Number
bits : 0 - 10 (11 bit)


TSZ

Total size register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSZ TSZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VTSZ HTSZ

VTSZ : Vertical total size of the display
bits : 0 - 11 (12 bit)

HTSZ : Horizontal total size of the display
bits : 16 - 27 (12 bit)


L1LUT

Layer 1 look up table register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1LUT L1LUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TB TG TR TADD

TB : Blue channel of a LUT entry
bits : 0 - 7 (8 bit)

TG : Green channel of a LUT entry
bits : 8 - 15 (8 bit)

TR : Red channel of a LUT entry
bits : 16 - 23 (8 bit)

TADD : Look Up Table Write Address
bits : 24 - 31 (8 bit)


CLT (CTL)

Control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLT CLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLIEN BDB GDB RDB DFEN CLKPS DEPS VPPS HPPS

TLIEN : TLI enable bit
bits : 0 - 0 (1 bit)

BDB : Blue channel Dither Bits Number
bits : 4 - 6 (3 bit)

GDB : Green channel Dither Bits Number
bits : 8 - 10 (3 bit)

RDB : Red channel Dither Bits Number
bits : 12 - 14 (3 bit)

DFEN : Dither Function Enable
bits : 16 - 16 (1 bit)

CLKPS : Pixel Clock Polarity Selection
bits : 28 - 28 (1 bit)

DEPS : Data Enable Polarity Selection
bits : 29 - 29 (1 bit)

VPPS : Vertical Pulse Polarity Selection
bits : 30 - 30 (1 bit)

HPPS : Horizontal Pulse Polarity Selection
bits : 31 - 31 (1 bit)


RL

Reload layer register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RL RL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RQR FBR

RQR : Request Reload
bits : 0 - 0 (1 bit)

FBR : Frame Blank Reload
bits : 1 - 1 (1 bit)


BGC

Background color register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BGC BGC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BVB BVG BVR

BVB : Background value blue
bits : 0 - 7 (8 bit)

BVG : Background value green
bits : 8 - 15 (8 bit)

BVR : Background value red
bits : 16 - 23 (8 bit)


INTEN

Interrupt enable register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LMIE FEIE TEIE LCRIE

LMIE : Line Mark Interrupt Enable
bits : 0 - 0 (1 bit)

FEIE : FIFO Error Interrupt Enable
bits : 1 - 1 (1 bit)

TEIE : Transaction Error Interrupt Enable
bits : 2 - 2 (1 bit)

LCRIE : Layer Configuration Reloaded Interrupt Enable
bits : 3 - 3 (1 bit)


INTF

Interrupt flag register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTF INTF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LMF FEF TEF LCRF

LMF : Line Mark Flag
bits : 0 - 0 (1 bit)

FEF : FIFO Error Flag
bits : 1 - 1 (1 bit)

TEF : Transaction Error Flag
bits : 2 - 2 (1 bit)

LCRF : Layer Configuration Reloaded Flag
bits : 3 - 3 (1 bit)


INTC

Interrupt flag clear register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INTC INTC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LMC FEC TEC LCRC

LMC : Line Mark Flag Clear
bits : 0 - 0 (1 bit)

FEC : FIFO Error Flag Clear
bits : 1 - 1 (1 bit)

TEC : Transaction Error Flag Clear
bits : 2 - 2 (1 bit)

LCRC : Layer Configuration Reloaded Flag Clear
bits : 3 - 3 (1 bit)


LM

Line mark register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LM LM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LM

LM : Line Mark value
bits : 0 - 10 (11 bit)


CPPOS

Current pixel position register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPPOS CPPOS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VPOS HPOS

VPOS : Vertical position
bits : 0 - 15 (16 bit)

HPOS : Horizontal position
bits : 16 - 31 (16 bit)


STAT

Status register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDE HDE VS HS

VDE : Current VDE status
bits : 0 - 0 (1 bit)

HDE : Current HDE status
bits : 1 - 1 (1 bit)

VS : Current VS staus of the TLI
bits : 2 - 2 (1 bit)

HS : Current HS staus of the TLI
bits : 3 - 3 (1 bit)


SPSZ

Synchronous pulse size register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPSZ SPSZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VPSZ HPSZ

VPSZ : size of vertical synchronous pluse
bits : 0 - 11 (12 bit)

HPSZ : size of horizontal synchronous pluse
bits : 16 - 27 (12 bit)


L0CTL

Layer 0 control register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L0CTL L0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEN CKEYEN LUTEN

LEN : Layer enable
bits : 0 - 0 (1 bit)

CKEYEN : Color keying enable
bits : 1 - 1 (1 bit)

LUTEN : LUT enable
bits : 4 - 4 (1 bit)


L0HPOS

Layer 0 horizontal position parameters register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L0HPOS L0HPOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WLP WRP

WLP : Window left position
bits : 0 - 11 (12 bit)

WRP : Window right position
bits : 16 - 27 (12 bit)


L0VPOS

Layer 0 vertical position parameters register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L0VPOS L0VPOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WTP WBP

WTP : Window top position
bits : 0 - 11 (12 bit)

WBP : Window bottom position
bits : 16 - 27 (12 bit)


L0CKEY

Layer 0 color key register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L0CKEY L0CKEY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKEYB CKEYG CKEYR

CKEYB : Color Key Blue
bits : 0 - 7 (8 bit)

CKEYG : Color Key Green
bits : 8 - 15 (8 bit)

CKEYR : Color Key Red
bits : 16 - 23 (8 bit)


L0PPF

Layer 0 packeted pixel format register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L0PPF L0PPF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPF

PPF : Packeted Pixel Format
bits : 0 - 2 (3 bit)


L0SA

Layer 0 specified alpha register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L0SA L0SA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Specified alpha
bits : 0 - 7 (8 bit)


L0DC

Layer 0 default color register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L0DC L0DC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCB DCG DCR DCA

DCB : The default color blue
bits : 0 - 7 (8 bit)

DCG : The default color green
bits : 8 - 15 (8 bit)

DCR : The default color red
bits : 16 - 23 (8 bit)

DCA : The default color ALPHA
bits : 24 - 31 (8 bit)


L0BLEND

Layer 0 blending register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L0BLEND L0BLEND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACF2 ACF1

ACF2 : Alpha Calculation Factor 2 of Blending Method
bits : 0 - 2 (3 bit)

ACF1 : Alpha Calculation Factor 1 of Blending Method
bits : 8 - 10 (3 bit)


L0FBADDR

Layer 0 frame base address register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L0FBADDR L0FBADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FBADD

FBADD : Frame Buffer base Address
bits : 0 - 31 (32 bit)


L0FLLEN

Layer 0 frame line length register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L0FLLEN L0FLLEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLL STDOFF

FLL : Frame Line Length
bits : 0 - 13 (14 bit)

STDOFF : Frame Buffer Stride Offset
bits : 16 - 29 (14 bit)


L0FTLN

Layer 0 frame total line number register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L0FTLN L0FTLN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTLN

FTLN : Frame Total Line Number
bits : 0 - 10 (11 bit)


BPSZ

Back-porch size register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BPSZ BPSZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBPSZ HBPSZ

VBPSZ : Size of the vertical back porch plus synchronous pulse
bits : 0 - 11 (12 bit)

HBPSZ : Size of the horizontal back porch plus synchronous pulse
bits : 16 - 27 (12 bit)


L0LUT

Layer 0 look up table register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L0LUT L0LUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TB TG TR TADD

TB : Blue channel of a LUT entry
bits : 0 - 7 (8 bit)

TG : Green channel of a LUT entry
bits : 8 - 15 (8 bit)

TR : Red Channel of a LUT entry
bits : 16 - 23 (8 bit)

TADD : Look Up Table Write Address
bits : 24 - 31 (8 bit)



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