\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
host control register (HCTL)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPDFSLS : Speed limited to FS and LS
bits : 2 - 2 (1 bit)
access : read-write
Host periodic transmit FIFO/queue status register (HPTFQSTAT)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTXFS : Periodic transmit data FIFO space available
bits : 0 - 15 (16 bit)
access : read-only
PTXREQS : Periodic Tx request queue space
bits : 16 - 23 (8 bit)
access : read-only
PTXREQT : Top of the periodic transmit request queue
bits : 24 - 31 (8 bit)
access : read-only
host channel-0 control register (HCH0CTL)
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
MPC : Multiple packet count
bits : 20 - 21 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-0 split transaction control register (HCH0STCTL)
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Port address
bits : 0 - 6 (7 bit)
HADDR : HUB address
bits : 7 - 13 (7 bit)
ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)
CSPLT : Complete split enable
bits : 16 - 16 (1 bit)
SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)
host channel-0 interrupt flag register (HCH0INTF)
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer completed
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
DMAER : DMA Error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : NYET
bits : 6 - 6 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-0 interrupt enable register (HCH0INTEN)
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-0 transfer length register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
PING : Ping token request
bits : 31 - 31 (1 bit)
host channel-0 DMA address register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
host channel-1 control register (HCH1CTL)
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
MPC : Multiple packet count
bits : 20 - 21 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-1 split transaction control register (HCH1STCTL)
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Port address
bits : 0 - 6 (7 bit)
HADDR : HUB address
bits : 7 - 13 (7 bit)
ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)
CSPLT : Complete split enable
bits : 16 - 16 (1 bit)
SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)
host channel-1 interrupt flag register (HCH1INTF)
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer completed
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
DMAER : DMA Error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : NYET
bits : 6 - 6 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-1 interrupt enable register (HCH1INTEN)
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-1 transfer length register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
PING : Ping token request
bits : 31 - 31 (1 bit)
host channel-1 DMA address register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
Host all channels interrupt register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HACHINT : Host all channel interrupts
bits : 0 - 11 (12 bit)
host channel-2 control register (HCH2CTL)
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
MPC : Multiple packet count
bits : 20 - 21 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-2 split transaction control register (HCH2STCTL)
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Port address
bits : 0 - 6 (7 bit)
HADDR : HUB address
bits : 7 - 13 (7 bit)
ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)
CSPLT : Complete split enable
bits : 16 - 16 (1 bit)
SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)
host channel-2 interrupt flag register (HCH2INTF)
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer completed
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
DMAER : DMA Error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : NYET
bits : 6 - 6 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-2 interrupt enable register (HCH2INTEN)
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-2 transfer length register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
PING : Ping token request
bits : 31 - 31 (1 bit)
host channel-2 DMA address register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
host channel-3 control register (HCH3CTL)
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
MPC : Multiple packet count
bits : 20 - 21 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-3 split transaction control register (HCH3STCTL)
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Port address
bits : 0 - 6 (7 bit)
HADDR : HUB address
bits : 7 - 13 (7 bit)
ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)
CSPLT : Complete split enable
bits : 16 - 16 (1 bit)
SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)
host channel-3 interrupt flag register (HCH3INTF)
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer completed
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
DMAER : DMA Error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : NYET
bits : 6 - 6 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-3 interrupt enable register (HCH3INTEN)
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-3 transfer length register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
PING : Ping token request
bits : 31 - 31 (1 bit)
host channel-3 DMA address register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
host all channels interrupt mask register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CINTEN : Channel interrupt enable
bits : 0 - 11 (12 bit)
host channel-4 control register (HCH4CTL)
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
MPC : Multiple packet count
bits : 20 - 21 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-4 split transaction control register (HCH4STCTL)
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Port address
bits : 0 - 6 (7 bit)
HADDR : HUB address
bits : 7 - 13 (7 bit)
ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)
CSPLT : Complete split enable
bits : 16 - 16 (1 bit)
SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)
host channel-4 interrupt flag register (HCH4INTF)
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer completed
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
DMAER : DMA Error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : NYET
bits : 6 - 6 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-4 interrupt enable register (HCH4INTEN)
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-4 transfer length register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
PING : Ping token request
bits : 31 - 31 (1 bit)
host channel-4 DMA address register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
host channel-5 control register (HCH5CTL)
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
MPC : Multiple packet count
bits : 20 - 21 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-5 split transaction control register (HCH5STCTL)
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Port address
bits : 0 - 6 (7 bit)
HADDR : HUB address
bits : 7 - 13 (7 bit)
ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)
CSPLT : Complete split enable
bits : 16 - 16 (1 bit)
SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)
host channel-5 interrupt flag register (HCH5INTF)
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer completed
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
DMAER : DMA Error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : NYET
bits : 6 - 6 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-5 interrupt enable register (HCH5INTEN)
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-5 transfer length register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
PING : Ping token request
bits : 31 - 31 (1 bit)
host channel-5 DMA address register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
host channel-6 control register (HCH6CTL)
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
MPC : Multiple packet count
bits : 20 - 21 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-6 split transaction control register (HCH6STCTL)
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Port address
bits : 0 - 6 (7 bit)
HADDR : HUB address
bits : 7 - 13 (7 bit)
ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)
CSPLT : Complete split enable
bits : 16 - 16 (1 bit)
SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)
host channel-6 interrupt flag register (HCH6INTF)
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer completed
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
DMAER : DMA Error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : NYET
bits : 6 - 6 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-6 interrupt enable register (HCH6INTEN)
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-6 transfer length register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
PING : Ping token request
bits : 31 - 31 (1 bit)
host channel-6 DMA address register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
host channel-7 control register (HCH7CTL)
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
MPC : Multiple packet count
bits : 20 - 21 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-7 split transaction control register (HCH7STCTL)
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Port address
bits : 0 - 6 (7 bit)
HADDR : HUB address
bits : 7 - 13 (7 bit)
ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)
CSPLT : Complete split enable
bits : 16 - 16 (1 bit)
SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)
host channel-7 interrupt flag register (HCH7INTF)
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer completed
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
DMAER : DMA Error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : NYET
bits : 6 - 6 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-7 interrupt enable register (HCH7INTEN)
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-7 transfer length register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
PING : Ping token request
bits : 31 - 31 (1 bit)
host channel-7 DMA address register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
host channel-8 control register (HCH8CTL)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
MPC : Multiple packet count
bits : 20 - 21 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-8 split transaction control register (HCH8STCTL)
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Port address
bits : 0 - 6 (7 bit)
HADDR : HUB address
bits : 7 - 13 (7 bit)
ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)
CSPLT : Complete split enable
bits : 16 - 16 (1 bit)
SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)
host channel-8 interrupt flag register (HCH8INTF)
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer completed
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
DMAER : DMA Error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : NYET
bits : 6 - 6 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-8 interrupt enable register (HCH8INTEN)
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-8 transfer length register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
PING : Ping token request
bits : 31 - 31 (1 bit)
host channel-8 DMA address register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
host channel-9 control register (HCH9CTL)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
MPC : Multiple packet count
bits : 20 - 21 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-9 split transaction control register (HCH9STCTL)
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Port address
bits : 0 - 6 (7 bit)
HADDR : HUB address
bits : 7 - 13 (7 bit)
ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)
CSPLT : Complete split enable
bits : 16 - 16 (1 bit)
SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)
host channel-9 interrupt flag register (HCH9INTF)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer completed
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
DMAER : DMA Error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : NYET
bits : 6 - 6 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-9 interrupt enable register (HCH9INTEN)
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-9 transfer length register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
PING : Ping token request
bits : 31 - 31 (1 bit)
host channel-9 DMA address register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
host channel-10 control register (HCH10CTL)
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
MPC : Multiple packet count
bits : 20 - 21 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-10 split transaction control register (HCH10STCTL)
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Port address
bits : 0 - 6 (7 bit)
HADDR : HUB address
bits : 7 - 13 (7 bit)
ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)
CSPLT : Complete split enable
bits : 16 - 16 (1 bit)
SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)
host channel-10 interrupt flag register (HCH10INTF)
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer completed
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
DMAER : DMA Error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : NYET
bits : 6 - 6 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-10 interrupt enable register (HCH10INTEN)
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-10 transfer length register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
PING : Ping token request
bits : 31 - 31 (1 bit)
host channel-10 DMA address register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
host channel-11 control register (HCH11CTL)
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPL : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSD : Low-speed device
bits : 17 - 17 (1 bit)
EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)
MPC : Multiple packet count
bits : 20 - 21 (2 bit)
DAR : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CDIS : Channel disable
bits : 30 - 30 (1 bit)
CEN : Channel enable
bits : 31 - 31 (1 bit)
host channel-11 split transaction control register (HCH11STCTL)
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADDR : Port address
bits : 0 - 6 (7 bit)
HADDR : HUB address
bits : 7 - 13 (7 bit)
ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)
CSPLT : Complete split enable
bits : 16 - 16 (1 bit)
SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)
host channel-11 interrupt flag register (HCH11INTF)
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TF : Transfer completed
bits : 0 - 0 (1 bit)
CH : Channel halted
bits : 1 - 1 (1 bit)
DMAER : DMA Error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : NYET
bits : 6 - 6 (1 bit)
USBER : USB bus error
bits : 7 - 7 (1 bit)
BBER : Babble error
bits : 8 - 8 (1 bit)
REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)
DTER : Data toggle error
bits : 10 - 10 (1 bit)
host channel-11 interrupt enable register (HCH11INTEN)
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)
CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)
DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)
STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)
NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)
ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)
NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)
USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)
BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)
REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)
DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)
host channel-11 transfer length register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLEN : Transfer length
bits : 0 - 18 (19 bit)
PCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
PING : Ping token request
bits : 31 - 31 (1 bit)
host channel-11 DMA address register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
Host frame interval register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRI : Frame interval
bits : 0 - 15 (16 bit)
host port control and status register (HPCS)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCST : Port connect status
bits : 0 - 0 (1 bit)
access : read-only
PCD : Port connect detected
bits : 1 - 1 (1 bit)
access : read-write
PE : Port enable
bits : 2 - 2 (1 bit)
access : read-write
PEDC : Port enable/disable change
bits : 3 - 3 (1 bit)
access : read-write
PREM : Port resume
bits : 6 - 6 (1 bit)
access : read-write
PSP : Port suspend
bits : 7 - 7 (1 bit)
access : read-write
PRST : Port reset
bits : 8 - 8 (1 bit)
access : read-write
PLST : Port line status
bits : 10 - 11 (2 bit)
access : read-only
PP : Port power
bits : 12 - 12 (1 bit)
access : read-write
PS : Port speed
bits : 17 - 18 (2 bit)
access : read-only
host frame number/frame time remaining register (HFINFR)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRNUM : Frame number
bits : 0 - 15 (16 bit)
FRT : Frame remaining time
bits : 16 - 31 (16 bit)
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