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USB_HS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

HCTL

HPTFQSTAT

HCH0CTL

HCH0STCTL

HCH0INTF

HCH0INTEN

HCH0LEN

HCH0DMAADDR

HCH1CTL

HCH1STCTL

HCH1INTF

HCH1INTEN

HCH1LEN

HCH1DMAADDR

HACHINT

HCH2CTL

HCH2STCTL

HCH2INTF

HCH2INTEN

HCH2LEN

HCH2DMAADDR

HCH3CTL

HCH3STCTL

HCH3INTF

HCH3INTEN

HCH3LEN

HCH3DMAADDR

HACHINTEN

HCH4CTL

HCH4STCTL

HCH4INTF

HCH4INTEN

HCH4LEN

HCH4DMAADDR

HCH5CTL

HCH5STCTL

HCH5INTF

HCH5INTEN

HCH5LEN

HCH5DMAADDR

HCH6CTL

HCH6STCTL

HCH6INTF

HCH6INTEN

HCH6LEN

HCH6DMAADDR

HCH7CTL

HCH7STCTL

HCH7INTF

HCH7INTEN

HCH7LEN

HCH7DMAADDR

HCH8CTL

HCH8STCTL

HCH8INTF

HCH8INTEN

HCH8LEN

HCH8DMAADDR

HCH9CTL

HCH9STCTL

HCH9INTF

HCH9INTEN

HCH9LEN

HCH9DMAADDR

HCH10CTL

HCH10STCTL

HCH10INTF

HCH10INTEN

HCH10LEN

HCH10DMAADDR

HCH11CTL

HCH11STCTL

HCH11INTF

HCH11INTEN

HCH11LEN

HCH11DMAADDR

HFT

HPCS

HFINFR


HCTL

host control register (HCTL)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCTL HCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPDFSLS

SPDFSLS : Speed limited to FS and LS
bits : 2 - 2 (1 bit)
access : read-write


HPTFQSTAT

Host periodic transmit FIFO/queue status register (HPTFQSTAT)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPTFQSTAT HPTFQSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTXFS PTXREQS PTXREQT

PTXFS : Periodic transmit data FIFO space available
bits : 0 - 15 (16 bit)
access : read-only

PTXREQS : Periodic Tx request queue space
bits : 16 - 23 (8 bit)
access : read-only

PTXREQT : Top of the periodic transmit request queue
bits : 24 - 31 (8 bit)
access : read-only


HCH0CTL

host channel-0 control register (HCH0CTL)
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH0CTL HCH0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE MPC DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

MPC : Multiple packet count
bits : 20 - 21 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH0STCTL

host channel-0 split transaction control register (HCH0STCTL)
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH0STCTL HCH0STCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR HADDR ISOPCE CSPLT SPLEN

PADDR : Port address
bits : 0 - 6 (7 bit)

HADDR : HUB address
bits : 7 - 13 (7 bit)

ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)

CSPLT : Complete split enable
bits : 16 - 16 (1 bit)

SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)


HCH0INTF

host channel-0 interrupt flag register (HCH0INTF)
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH0INTF HCH0INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH DMAER STALL NAK ACK NYET USBER BBER REQOVR DTER

TF : Transfer completed
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

DMAER : DMA Error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : NYET
bits : 6 - 6 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH0INTEN

host channel-0 interrupt enable register (HCH0INTEN)
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH0INTEN HCH0INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE DMAERIE STALLIE NAKIE ACKIE NYETIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH0LEN

host channel-0 transfer length register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH0LEN HCH0LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID PING

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)

PING : Ping token request
bits : 31 - 31 (1 bit)


HCH0DMAADDR

host channel-0 DMA address register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH0DMAADDR HCH0DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


HCH1CTL

host channel-1 control register (HCH1CTL)
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH1CTL HCH1CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE MPC DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

MPC : Multiple packet count
bits : 20 - 21 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH1STCTL

host channel-1 split transaction control register (HCH1STCTL)
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH1STCTL HCH1STCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR HADDR ISOPCE CSPLT SPLEN

PADDR : Port address
bits : 0 - 6 (7 bit)

HADDR : HUB address
bits : 7 - 13 (7 bit)

ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)

CSPLT : Complete split enable
bits : 16 - 16 (1 bit)

SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)


HCH1INTF

host channel-1 interrupt flag register (HCH1INTF)
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH1INTF HCH1INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH DMAER STALL NAK ACK NYET USBER BBER REQOVR DTER

TF : Transfer completed
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

DMAER : DMA Error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : NYET
bits : 6 - 6 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH1INTEN

host channel-1 interrupt enable register (HCH1INTEN)
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH1INTEN HCH1INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE DMAERIE STALLIE NAKIE ACKIE NYETIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH1LEN

host channel-1 transfer length register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH1LEN HCH1LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID PING

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)

PING : Ping token request
bits : 31 - 31 (1 bit)


HCH1DMAADDR

host channel-1 DMA address register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH1DMAADDR HCH1DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


HACHINT

Host all channels interrupt register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HACHINT HACHINT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HACHINT

HACHINT : Host all channel interrupts
bits : 0 - 11 (12 bit)


HCH2CTL

host channel-2 control register (HCH2CTL)
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH2CTL HCH2CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE MPC DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

MPC : Multiple packet count
bits : 20 - 21 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH2STCTL

host channel-2 split transaction control register (HCH2STCTL)
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH2STCTL HCH2STCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR HADDR ISOPCE CSPLT SPLEN

PADDR : Port address
bits : 0 - 6 (7 bit)

HADDR : HUB address
bits : 7 - 13 (7 bit)

ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)

CSPLT : Complete split enable
bits : 16 - 16 (1 bit)

SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)


HCH2INTF

host channel-2 interrupt flag register (HCH2INTF)
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH2INTF HCH2INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH DMAER STALL NAK ACK NYET USBER BBER REQOVR DTER

TF : Transfer completed
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

DMAER : DMA Error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : NYET
bits : 6 - 6 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH2INTEN

host channel-2 interrupt enable register (HCH2INTEN)
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH2INTEN HCH2INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE DMAERIE STALLIE NAKIE ACKIE NYETIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH2LEN

host channel-2 transfer length register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH2LEN HCH2LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID PING

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)

PING : Ping token request
bits : 31 - 31 (1 bit)


HCH2DMAADDR

host channel-2 DMA address register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH2DMAADDR HCH2DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


HCH3CTL

host channel-3 control register (HCH3CTL)
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH3CTL HCH3CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE MPC DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

MPC : Multiple packet count
bits : 20 - 21 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH3STCTL

host channel-3 split transaction control register (HCH3STCTL)
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH3STCTL HCH3STCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR HADDR ISOPCE CSPLT SPLEN

PADDR : Port address
bits : 0 - 6 (7 bit)

HADDR : HUB address
bits : 7 - 13 (7 bit)

ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)

CSPLT : Complete split enable
bits : 16 - 16 (1 bit)

SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)


HCH3INTF

host channel-3 interrupt flag register (HCH3INTF)
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH3INTF HCH3INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH DMAER STALL NAK ACK NYET USBER BBER REQOVR DTER

TF : Transfer completed
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

DMAER : DMA Error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : NYET
bits : 6 - 6 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH3INTEN

host channel-3 interrupt enable register (HCH3INTEN)
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH3INTEN HCH3INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE DMAERIE STALLIE NAKIE ACKIE NYETIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH3LEN

host channel-3 transfer length register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH3LEN HCH3LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID PING

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)

PING : Ping token request
bits : 31 - 31 (1 bit)


HCH3DMAADDR

host channel-3 DMA address register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH3DMAADDR HCH3DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


HACHINTEN

host all channels interrupt mask register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HACHINTEN HACHINTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CINTEN

CINTEN : Channel interrupt enable
bits : 0 - 11 (12 bit)


HCH4CTL

host channel-4 control register (HCH4CTL)
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH4CTL HCH4CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE MPC DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

MPC : Multiple packet count
bits : 20 - 21 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH4STCTL

host channel-4 split transaction control register (HCH4STCTL)
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH4STCTL HCH4STCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR HADDR ISOPCE CSPLT SPLEN

PADDR : Port address
bits : 0 - 6 (7 bit)

HADDR : HUB address
bits : 7 - 13 (7 bit)

ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)

CSPLT : Complete split enable
bits : 16 - 16 (1 bit)

SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)


HCH4INTF

host channel-4 interrupt flag register (HCH4INTF)
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH4INTF HCH4INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH DMAER STALL NAK ACK NYET USBER BBER REQOVR DTER

TF : Transfer completed
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

DMAER : DMA Error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : NYET
bits : 6 - 6 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH4INTEN

host channel-4 interrupt enable register (HCH4INTEN)
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH4INTEN HCH4INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE DMAERIE STALLIE NAKIE ACKIE NYETIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH4LEN

host channel-4 transfer length register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH4LEN HCH4LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID PING

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)

PING : Ping token request
bits : 31 - 31 (1 bit)


HCH4DMAADDR

host channel-4 DMA address register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH4DMAADDR HCH4DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


HCH5CTL

host channel-5 control register (HCH5CTL)
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH5CTL HCH5CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE MPC DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

MPC : Multiple packet count
bits : 20 - 21 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH5STCTL

host channel-5 split transaction control register (HCH5STCTL)
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH5STCTL HCH5STCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR HADDR ISOPCE CSPLT SPLEN

PADDR : Port address
bits : 0 - 6 (7 bit)

HADDR : HUB address
bits : 7 - 13 (7 bit)

ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)

CSPLT : Complete split enable
bits : 16 - 16 (1 bit)

SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)


HCH5INTF

host channel-5 interrupt flag register (HCH5INTF)
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH5INTF HCH5INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH DMAER STALL NAK ACK NYET USBER BBER REQOVR DTER

TF : Transfer completed
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

DMAER : DMA Error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : NYET
bits : 6 - 6 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH5INTEN

host channel-5 interrupt enable register (HCH5INTEN)
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH5INTEN HCH5INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE DMAERIE STALLIE NAKIE ACKIE NYETIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH5LEN

host channel-5 transfer length register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH5LEN HCH5LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID PING

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)

PING : Ping token request
bits : 31 - 31 (1 bit)


HCH5DMAADDR

host channel-5 DMA address register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH5DMAADDR HCH5DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


HCH6CTL

host channel-6 control register (HCH6CTL)
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH6CTL HCH6CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE MPC DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

MPC : Multiple packet count
bits : 20 - 21 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH6STCTL

host channel-6 split transaction control register (HCH6STCTL)
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH6STCTL HCH6STCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR HADDR ISOPCE CSPLT SPLEN

PADDR : Port address
bits : 0 - 6 (7 bit)

HADDR : HUB address
bits : 7 - 13 (7 bit)

ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)

CSPLT : Complete split enable
bits : 16 - 16 (1 bit)

SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)


HCH6INTF

host channel-6 interrupt flag register (HCH6INTF)
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH6INTF HCH6INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH DMAER STALL NAK ACK NYET USBER BBER REQOVR DTER

TF : Transfer completed
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

DMAER : DMA Error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : NYET
bits : 6 - 6 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH6INTEN

host channel-6 interrupt enable register (HCH6INTEN)
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH6INTEN HCH6INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE DMAERIE STALLIE NAKIE ACKIE NYETIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH6LEN

host channel-6 transfer length register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH6LEN HCH6LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID PING

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)

PING : Ping token request
bits : 31 - 31 (1 bit)


HCH6DMAADDR

host channel-6 DMA address register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH6DMAADDR HCH6DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


HCH7CTL

host channel-7 control register (HCH7CTL)
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH7CTL HCH7CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE MPC DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

MPC : Multiple packet count
bits : 20 - 21 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH7STCTL

host channel-7 split transaction control register (HCH7STCTL)
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH7STCTL HCH7STCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR HADDR ISOPCE CSPLT SPLEN

PADDR : Port address
bits : 0 - 6 (7 bit)

HADDR : HUB address
bits : 7 - 13 (7 bit)

ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)

CSPLT : Complete split enable
bits : 16 - 16 (1 bit)

SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)


HCH7INTF

host channel-7 interrupt flag register (HCH7INTF)
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH7INTF HCH7INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH DMAER STALL NAK ACK NYET USBER BBER REQOVR DTER

TF : Transfer completed
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

DMAER : DMA Error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : NYET
bits : 6 - 6 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH7INTEN

host channel-7 interrupt enable register (HCH7INTEN)
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH7INTEN HCH7INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE DMAERIE STALLIE NAKIE ACKIE NYETIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH7LEN

host channel-7 transfer length register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH7LEN HCH7LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID PING

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)

PING : Ping token request
bits : 31 - 31 (1 bit)


HCH7DMAADDR

host channel-7 DMA address register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH7DMAADDR HCH7DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


HCH8CTL

host channel-8 control register (HCH8CTL)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH8CTL HCH8CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE MPC DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

MPC : Multiple packet count
bits : 20 - 21 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH8STCTL

host channel-8 split transaction control register (HCH8STCTL)
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH8STCTL HCH8STCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR HADDR ISOPCE CSPLT SPLEN

PADDR : Port address
bits : 0 - 6 (7 bit)

HADDR : HUB address
bits : 7 - 13 (7 bit)

ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)

CSPLT : Complete split enable
bits : 16 - 16 (1 bit)

SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)


HCH8INTF

host channel-8 interrupt flag register (HCH8INTF)
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH8INTF HCH8INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH DMAER STALL NAK ACK NYET USBER BBER REQOVR DTER

TF : Transfer completed
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

DMAER : DMA Error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : NYET
bits : 6 - 6 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH8INTEN

host channel-8 interrupt enable register (HCH8INTEN)
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH8INTEN HCH8INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE DMAERIE STALLIE NAKIE ACKIE NYETIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH8LEN

host channel-8 transfer length register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH8LEN HCH8LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID PING

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)

PING : Ping token request
bits : 31 - 31 (1 bit)


HCH8DMAADDR

host channel-8 DMA address register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH8DMAADDR HCH8DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


HCH9CTL

host channel-9 control register (HCH9CTL)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH9CTL HCH9CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE MPC DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

MPC : Multiple packet count
bits : 20 - 21 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH9STCTL

host channel-9 split transaction control register (HCH9STCTL)
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH9STCTL HCH9STCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR HADDR ISOPCE CSPLT SPLEN

PADDR : Port address
bits : 0 - 6 (7 bit)

HADDR : HUB address
bits : 7 - 13 (7 bit)

ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)

CSPLT : Complete split enable
bits : 16 - 16 (1 bit)

SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)


HCH9INTF

host channel-9 interrupt flag register (HCH9INTF)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH9INTF HCH9INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH DMAER STALL NAK ACK NYET USBER BBER REQOVR DTER

TF : Transfer completed
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

DMAER : DMA Error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : NYET
bits : 6 - 6 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH9INTEN

host channel-9 interrupt enable register (HCH9INTEN)
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH9INTEN HCH9INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE DMAERIE STALLIE NAKIE ACKIE NYETIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH9LEN

host channel-9 transfer length register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH9LEN HCH9LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID PING

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)

PING : Ping token request
bits : 31 - 31 (1 bit)


HCH9DMAADDR

host channel-9 DMA address register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH9DMAADDR HCH9DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


HCH10CTL

host channel-10 control register (HCH10CTL)
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH10CTL HCH10CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE MPC DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

MPC : Multiple packet count
bits : 20 - 21 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH10STCTL

host channel-10 split transaction control register (HCH10STCTL)
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH10STCTL HCH10STCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR HADDR ISOPCE CSPLT SPLEN

PADDR : Port address
bits : 0 - 6 (7 bit)

HADDR : HUB address
bits : 7 - 13 (7 bit)

ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)

CSPLT : Complete split enable
bits : 16 - 16 (1 bit)

SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)


HCH10INTF

host channel-10 interrupt flag register (HCH10INTF)
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH10INTF HCH10INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH DMAER STALL NAK ACK NYET USBER BBER REQOVR DTER

TF : Transfer completed
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

DMAER : DMA Error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : NYET
bits : 6 - 6 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH10INTEN

host channel-10 interrupt enable register (HCH10INTEN)
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH10INTEN HCH10INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE DMAERIE STALLIE NAKIE ACKIE NYETIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH10LEN

host channel-10 transfer length register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH10LEN HCH10LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID PING

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)

PING : Ping token request
bits : 31 - 31 (1 bit)


HCH10DMAADDR

host channel-10 DMA address register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH10DMAADDR HCH10DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


HCH11CTL

host channel-11 control register (HCH11CTL)
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH11CTL HCH11CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPL EPNUM EPDIR LSD EPTYPE MPC DAR ODDFRM CDIS CEN

MPL : Maximum packet size
bits : 0 - 10 (11 bit)

EPNUM : Endpoint number
bits : 11 - 14 (4 bit)

EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)

LSD : Low-speed device
bits : 17 - 17 (1 bit)

EPTYPE : Endpoint type
bits : 18 - 19 (2 bit)

MPC : Multiple packet count
bits : 20 - 21 (2 bit)

DAR : Device address
bits : 22 - 28 (7 bit)

ODDFRM : Odd frame
bits : 29 - 29 (1 bit)

CDIS : Channel disable
bits : 30 - 30 (1 bit)

CEN : Channel enable
bits : 31 - 31 (1 bit)


HCH11STCTL

host channel-11 split transaction control register (HCH11STCTL)
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH11STCTL HCH11STCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR HADDR ISOPCE CSPLT SPLEN

PADDR : Port address
bits : 0 - 6 (7 bit)

HADDR : HUB address
bits : 7 - 13 (7 bit)

ISOPCE : Isochronous OUT payload continuation encoding
bits : 14 - 15 (2 bit)

CSPLT : Complete split enable
bits : 16 - 16 (1 bit)

SPLEN : Enable high speed split transaction
bits : 31 - 31 (1 bit)


HCH11INTF

host channel-11 interrupt flag register (HCH11INTF)
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH11INTF HCH11INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF CH DMAER STALL NAK ACK NYET USBER BBER REQOVR DTER

TF : Transfer completed
bits : 0 - 0 (1 bit)

CH : Channel halted
bits : 1 - 1 (1 bit)

DMAER : DMA Error
bits : 2 - 2 (1 bit)

STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)

NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)

ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)

NYET : NYET
bits : 6 - 6 (1 bit)

USBER : USB bus error
bits : 7 - 7 (1 bit)

BBER : Babble error
bits : 8 - 8 (1 bit)

REQOVR : Request queue overrun
bits : 9 - 9 (1 bit)

DTER : Data toggle error
bits : 10 - 10 (1 bit)


HCH11INTEN

host channel-11 interrupt enable register (HCH11INTEN)
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH11INTEN HCH11INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIE CHIE DMAERIE STALLIE NAKIE ACKIE NYETIE USBERIE BBERIE REQOVRIE DTERIE

TFIE : Transfer finished interrupt enable
bits : 0 - 0 (1 bit)

CHIE : Channel halted interrupt enable
bits : 1 - 1 (1 bit)

DMAERIE : DMA error interrupt enable
bits : 2 - 2 (1 bit)

STALLIE : STALL interrupt enable
bits : 3 - 3 (1 bit)

NAKIE : NAK interrupt enable
bits : 4 - 4 (1 bit)

ACKIE : ACK interrupt enable
bits : 5 - 5 (1 bit)

NYETIE : NYET interrupt enable
bits : 6 - 6 (1 bit)

USBERIE : USB bus error interrupt enable
bits : 7 - 7 (1 bit)

BBERIE : Babble error interrupt enable
bits : 8 - 8 (1 bit)

REQOVRIE : request queue overrun interrupt enable
bits : 9 - 9 (1 bit)

DTERIE : Data toggle error interrupt enable
bits : 10 - 10 (1 bit)


HCH11LEN

host channel-11 transfer length register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH11LEN HCH11LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEN PCNT DPID PING

TLEN : Transfer length
bits : 0 - 18 (19 bit)

PCNT : Packet count
bits : 19 - 28 (10 bit)

DPID : Data PID
bits : 29 - 30 (2 bit)

PING : Ping token request
bits : 31 - 31 (1 bit)


HCH11DMAADDR

host channel-11 DMA address register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCH11DMAADDR HCH11DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA address
bits : 0 - 31 (32 bit)


HFT

Host frame interval register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFT HFT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRI

FRI : Frame interval
bits : 0 - 15 (16 bit)


HPCS

host port control and status register (HPCS)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPCS HPCS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCST PCD PE PEDC PREM PSP PRST PLST PP PS

PCST : Port connect status
bits : 0 - 0 (1 bit)
access : read-only

PCD : Port connect detected
bits : 1 - 1 (1 bit)
access : read-write

PE : Port enable
bits : 2 - 2 (1 bit)
access : read-write

PEDC : Port enable/disable change
bits : 3 - 3 (1 bit)
access : read-write

PREM : Port resume
bits : 6 - 6 (1 bit)
access : read-write

PSP : Port suspend
bits : 7 - 7 (1 bit)
access : read-write

PRST : Port reset
bits : 8 - 8 (1 bit)
access : read-write

PLST : Port line status
bits : 10 - 11 (2 bit)
access : read-only

PP : Port power
bits : 12 - 12 (1 bit)
access : read-write

PS : Port speed
bits : 17 - 18 (2 bit)
access : read-only


HFINFR

host frame number/frame time remaining register (HFINFR)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HFINFR HFINFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRNUM FRT

FRNUM : Frame number
bits : 0 - 15 (16 bit)

FRT : Frame remaining time
bits : 16 - 31 (16 bit)



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