\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
ADC State Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYF : ADC ready flag
bits : 0 - 0 (1 bit)
access : read-only
ESMPF : End of sampling flag
bits : 1 - 1 (1 bit)
access : read-only
ECF : End of conversion flag
bits : 2 - 2 (1 bit)
access : read-only
ESF : End of sequence flag
bits : 3 - 3 (1 bit)
access : read-only
OVRF : Overrun flag
bits : 4 - 4 (1 bit)
access : read-only
AWF : Analog watchdog flag
bits : 7 - 7 (1 bit)
access : read-only
ADC Configuration Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : ADC clock selection
bits : 30 - 31 (2 bit)
access : read-write
ADC Sampling time Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMPT : Sampling time
bits : 0 - 2 (3 bit)
access : read-write
ADC Analog Watchdog Threshold Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWTL : Analog watchdog low threshold
bits : 0 - 11 (12 bit)
access : read-write
AWTH : Analog watchdog high threshold
bits : 16 - 27 (12 bit)
access : read-write
ADC Channel Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN0 : Channel 0 enable
bits : 0 - 0 (1 bit)
access : read-write
CHEN1 : Channel 1 enable
bits : 1 - 1 (1 bit)
access : read-write
CHEN2 : Channel 2 enable
bits : 2 - 2 (1 bit)
access : read-write
CHEN3 : Channel 3 enable
bits : 3 - 3 (1 bit)
access : read-write
CHEN4 : Channel 4 enable
bits : 4 - 4 (1 bit)
access : read-write
CHEN5 : Channel 5 enable
bits : 5 - 5 (1 bit)
access : read-write
CHEN6 : Channel 6 enable
bits : 6 - 6 (1 bit)
access : read-write
CHEN7 : Channel 7 enable
bits : 7 - 7 (1 bit)
access : read-write
CHEN8 : Channel 8 enable
bits : 8 - 8 (1 bit)
access : read-write
CHEN9 : Channel 9 enable
bits : 9 - 9 (1 bit)
access : read-write
CHEN16 : Channel 16 enable
bits : 16 - 16 (1 bit)
access : read-write
CHEN17 : Channel 17 enable
bits : 17 - 17 (1 bit)
access : read-write
ADC Common Configuration Register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VINREFEN : VINREF signal to ADC enable
bits : 22 - 22 (1 bit)
access : read-write
TEMPSEN : Temperature sensor enable
bits : 23 - 23 (1 bit)
access : read-write
ADC Interrupt Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDYINTEN : ADC ready interrupt enable
bits : 0 - 0 (1 bit)
access : read-write
ESMPINTEN : End of sampling interrupt enable
bits : 1 - 1 (1 bit)
access : read-write
ECINTEN : End of conversion interrupt enable
bits : 2 - 2 (1 bit)
access : read-write
ESINTEN : End of sequence interrupt enable
bits : 3 - 3 (1 bit)
access : read-write
OVRINTEN : Overrun interrupt enable
bits : 4 - 4 (1 bit)
access : read-write
AWINTEN : Analog watchdog interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
ADC Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : ADC data
bits : 0 - 15 (16 bit)
access : read-only
ADC Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : ADC enable
bits : 0 - 0 (1 bit)
access : read-write
DIS : ADC disable
bits : 1 - 1 (1 bit)
access : read-write
START : ADC start command
bits : 2 - 2 (1 bit)
access : read-write
STP : ADC stop conversion command
bits : 4 - 4 (1 bit)
access : read-write
CAL : ADC calibration command
bits : 31 - 31 (1 bit)
access : read-write
ADC configuration Register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : Enable the DMA function of ADC
bits : 0 - 0 (1 bit)
access : read-write
DMAMOD : Mode of DMA of ADC
bits : 1 - 1 (1 bit)
access : read-write
DIR : Scanning direction of a sequence
bits : 2 - 2 (1 bit)
access : read-write
RES : Resolution of conversion
bits : 3 - 4 (2 bit)
access : read-write
ALIGN : Alignment of data
bits : 5 - 5 (1 bit)
access : read-write
EXTTRIG : External trigger selection
bits : 6 - 8 (3 bit)
access : read-write
TRIG : Trigger selection
bits : 10 - 11 (2 bit)
access : read-write
OVRW : Overrun write
bits : 12 - 12 (1 bit)
access : read-write
SEQCON : Sequence continuous mode
bits : 13 - 13 (1 bit)
access : read-write
WTRD : Wait to read mode
bits : 14 - 14 (1 bit)
access : read-write
AUTOPM : Automatic power management
bits : 15 - 15 (1 bit)
access : read-write
PAUSE : Pause mode
bits : 16 - 16 (1 bit)
access : read-write
AWSG : Analog watchdog Single channel mode
bits : 22 - 22 (1 bit)
access : read-write
AWEN : Analog watchdog enable
bits : 23 - 23 (1 bit)
access : read-write
AWCHSEL : Analog watchdog channel selection
bits : 26 - 30 (5 bit)
access : read-write
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