\n

DEBUG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

ID

CTL

FRZ0

FRZ1


ID

debug id code
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ID ID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEV_ID REV_ID

DEV_ID : Device identifier, indicates device family
bits : 0 - 11 (12 bit)
access : read-only

REV_ID : Revision identifier This field indicates the revision of the device
bits : 16 - 31 (16 bit)
access : read-only


CTL

debug in low power mode
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STP STB

STP : Debug Stop mode
bits : 1 - 1 (1 bit)
access : read-write

STB : Debug Standby mode
bits : 2 - 2 (1 bit)
access : read-write


FRZ0

configure if clock of I2C/FWDT/WWDT/RTC/TIMER stop when the core is halted
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRZ0 FRZ0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMERG1STP TIMERG2STP RTCSTP WWDTSTP FWDTSTP I2C1_SMBUSSTP

TIMERG1STP : TIMERG1 is stopped when the core is halted
bits : 1 - 1 (1 bit)
access : read-write

TIMERG2STP : TIMERG2 is stopped when the core is halted
bits : 8 - 8 (1 bit)
access : read-write

RTCSTP : RTC counter is stopped when the core is halted
bits : 10 - 10 (1 bit)
access : read-write

WWDTSTP : window watchdog timer stopped when core is halted
bits : 11 - 11 (1 bit)
access : read-write

FWDTSTP : Free running watchdog timer stopped when core is halted
bits : 12 - 12 (1 bit)
access : read-write

I2C1_SMBUSSTP : I2C1 SMBUS timeout mode stopped when core is halted
bits : 21 - 21 (1 bit)
access : read-write


FRZ1

configure if clock of timers stop when the core is halted
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRZ1 FRZ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMERA1STP TIMERG3STP TIMERG4STP

TIMERA1STP : TIMERA1 counter is stopped when the core is halted
bits : 11 - 11 (1 bit)
access : read-write

TIMERG3STP : TIMERG3 counter is stopped when the core is halted
bits : 17 - 17 (1 bit)
access : read-write

TIMERG4STP : TIMERG4 counter is stopped when the core is halted
bits : 18 - 18 (1 bit)
access : read-write



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