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DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

INTSTAT

PERIADDR1

MEMADDR1

CFG2

LEN2

PERIADDR2

MEMADDR2

CFG3

LEN3

PERIADDR3

MEMADDR3

INTCLR

CFG4

LEN4

PERIADDR4

MEMADDR4

CFG5

LEN5

PERIADDR5

MEMADDR5

CFG1

LEN1


INTSTAT

interrupt status
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTAT INTSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GINTF1 CINTF1 HINTF1 EINTF1 GINTF2 CINTF2 HINTF2 EINTF2 GINTF3 CINTF3 HINTF3 EINTF3 GINTF4 CINTF4 HINTF4 EINTF4 GINTF5 CINTF5 HINTF5 EINTF5

GINTF1 : channel1 global interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

CINTF1 : channel1 transfer complete flag
bits : 1 - 1 (1 bit)
access : read-only

HINTF1 : channel 1 half transfer flag
bits : 2 - 2 (1 bit)
access : read-only

EINTF1 : channel 1 transfer error flag
bits : 3 - 3 (1 bit)
access : read-only

GINTF2 : channel2 global interrupt flag
bits : 4 - 4 (1 bit)
access : read-only

CINTF2 : channel2 transfer complete flag
bits : 5 - 5 (1 bit)
access : read-only

HINTF2 : channel 2 half transfer flag
bits : 6 - 6 (1 bit)
access : read-only

EINTF2 : channel 2 transfer error flag
bits : 7 - 7 (1 bit)
access : read-only

GINTF3 : channel3 global interrupt flag
bits : 8 - 8 (1 bit)
access : read-only

CINTF3 : channel3 transfer complete flag
bits : 9 - 9 (1 bit)
access : read-only

HINTF3 : channel 3 half transfer flag
bits : 10 - 10 (1 bit)
access : read-only

EINTF3 : channel 3 transfer error flag
bits : 11 - 11 (1 bit)
access : read-only

GINTF4 : channel4 global interrupt flag
bits : 12 - 12 (1 bit)
access : read-only

CINTF4 : channel4 transfer complete flag
bits : 13 - 13 (1 bit)
access : read-only

HINTF4 : channel 4 half transfer flag
bits : 14 - 14 (1 bit)
access : read-only

EINTF4 : channel 4 transfer error flag
bits : 15 - 15 (1 bit)
access : read-only

GINTF5 : channel5 global interrupt flag
bits : 16 - 16 (1 bit)
access : read-only

CINTF5 : channel5 transfer complete flag
bits : 17 - 17 (1 bit)
access : read-only

HINTF5 : channel 5 half transfer flag
bits : 18 - 18 (1 bit)
access : read-only

EINTF5 : channel 5 transfer error flag
bits : 19 - 19 (1 bit)
access : read-only


PERIADDR1

channel 1 peripheral address
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERIADDR1 PERIADDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : channel 1 peripheral address
bits : 0 - 31 (32 bit)
access : read-write


MEMADDR1

channel 1 memory address
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMADDR1 MEMADDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : channel 1 memory address
bits : 0 - 31 (32 bit)
access : read-write


CFG2

channel 2 channel configuration
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG2 CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN CINTEN HINTEN EINTEN DIR CIR PERIINC MEMINC PERISZ MSZ PRI M2M

CHEN : channel enable
bits : 0 - 0 (1 bit)
access : read-write

CINTEN : transfer complete interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

HINTEN : half transfer interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

EINTEN : transfer error interrupt enable
bits : 3 - 3 (1 bit)
access : read-write

DIR : data transfer direction
bits : 4 - 4 (1 bit)
access : read-write

CIR : circular mode
bits : 5 - 5 (1 bit)
access : read-write

PERIINC : peripheral increment mode
bits : 6 - 6 (1 bit)
access : read-write

MEMINC : memory increment mode
bits : 7 - 7 (1 bit)
access : read-write

PERISZ : peripheral size
bits : 8 - 9 (2 bit)
access : read-write

MSZ : memory size
bits : 10 - 11 (2 bit)
access : read-write

PRI : channel priority level
bits : 12 - 13 (2 bit)
access : read-write

M2M : memory to memory mode
bits : 14 - 14 (1 bit)
access : read-write


LEN2

channel 2 transfer length
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LEN2 LEN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEN

LEN : channel 2 number of data to transfer
bits : 0 - 15 (16 bit)
access : read-write


PERIADDR2

channel 2 peripheral address
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERIADDR2 PERIADDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : channel 2 peripheral address
bits : 0 - 31 (32 bit)
access : read-write


MEMADDR2

channel 2 memory address
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMADDR2 MEMADDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : channel 2 memory address
bits : 0 - 31 (32 bit)
access : read-write


CFG3

channel 3 channel configuration
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG3 CFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN CINTEN HINTEN EINTEN DIR CIR PERIINC MEMINC PERISZ MSZ PRI M2M

CHEN : channel enable
bits : 0 - 0 (1 bit)
access : read-write

CINTEN : transfer complete interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

HINTEN : half transfer interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

EINTEN : transfer error interrupt enable
bits : 3 - 3 (1 bit)
access : read-write

DIR : data transfer direction
bits : 4 - 4 (1 bit)
access : read-write

CIR : circular mode
bits : 5 - 5 (1 bit)
access : read-write

PERIINC : peripheral increment mode
bits : 6 - 6 (1 bit)
access : read-write

MEMINC : memory increment mode
bits : 7 - 7 (1 bit)
access : read-write

PERISZ : peripheral size
bits : 8 - 9 (2 bit)
access : read-write

MSZ : memory size
bits : 10 - 11 (2 bit)
access : read-write

PRI : channel priority level
bits : 12 - 13 (2 bit)
access : read-write

M2M : memory to memory mode
bits : 14 - 14 (1 bit)
access : read-write


LEN3

channel 3 transfer length
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LEN3 LEN3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEN

LEN : channel 3 number of data to transfer
bits : 0 - 15 (16 bit)
access : read-write


PERIADDR3

channel 3 peripheral address
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERIADDR3 PERIADDR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : channel 3 peripheral address
bits : 0 - 31 (32 bit)
access : read-write


MEMADDR3

channel 3 memory address
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMADDR3 MEMADDR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : channel 3 memory address
bits : 0 - 31 (32 bit)
access : read-write


INTCLR

clear interrupt status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INTCLR INTCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GINTFCLR1 CINTFCLR1 HINTFCLR1 EINTFCLR1 GINTFCLR2 CINTFCLR2 HINTFCLR2 EINTFCLR2 GINTFCLR3 CINTFCLR3 HINTFCLR3 EINTFCLR3 GINTFCLR4 CINTFCLR4 HINTFCLR4 EINTFCLR4 GINTFCLR5 CINTFCLR5 HINTFCLR5 EINTFCLR5

GINTFCLR1 : channel1 global interrupt flag clear
bits : 0 - 0 (1 bit)
access : write-only

CINTFCLR1 : channel1 transfer complete flag clear
bits : 1 - 1 (1 bit)
access : write-only

HINTFCLR1 : channel 1 half transfer flag clear
bits : 2 - 2 (1 bit)
access : write-only

EINTFCLR1 : channel 1 transfer error flag clear
bits : 3 - 3 (1 bit)
access : write-only

GINTFCLR2 : channel2 global interrupt flag clear
bits : 4 - 4 (1 bit)
access : write-only

CINTFCLR2 : channel2 transfer complete flag clear
bits : 5 - 5 (1 bit)
access : write-only

HINTFCLR2 : channel 2 half transfer flag clear
bits : 6 - 6 (1 bit)
access : write-only

EINTFCLR2 : channel 2 transfer error flag clear
bits : 7 - 7 (1 bit)
access : write-only

GINTFCLR3 : channel3 global interrupt flag clear
bits : 8 - 8 (1 bit)
access : write-only

CINTFCLR3 : channel3 transfer complete flag clear
bits : 9 - 9 (1 bit)
access : write-only

HINTFCLR3 : channel 3 half transfer flag clear
bits : 10 - 10 (1 bit)
access : write-only

EINTFCLR3 : channel 3 transfer error flag clear
bits : 11 - 11 (1 bit)
access : write-only

GINTFCLR4 : channel4 global interrupt flag clear
bits : 12 - 12 (1 bit)
access : write-only

CINTFCLR4 : channel4 transfer complete flag clear
bits : 13 - 13 (1 bit)
access : write-only

HINTFCLR4 : channel 4 half transfer flag clear
bits : 14 - 14 (1 bit)
access : write-only

EINTFCLR4 : channel 4 transfer error flag clear
bits : 15 - 15 (1 bit)
access : write-only

GINTFCLR5 : channel5 global interrupt flag clear
bits : 16 - 16 (1 bit)
access : write-only

CINTFCLR5 : channel5 transfer complete flag clear
bits : 17 - 17 (1 bit)
access : write-only

HINTFCLR5 : channel 5 half transfer flag clear
bits : 18 - 18 (1 bit)
access : write-only

EINTFCLR5 : channel 5 transfer error flag clear
bits : 19 - 19 (1 bit)
access : write-only


CFG4

channel 4 channel configuration
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG4 CFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN CINTEN HINTEN EINTEN DIR CIR PERIINC MEMINC PERISZ MSZ PRI M2M

CHEN : channel enable
bits : 0 - 0 (1 bit)
access : read-write

CINTEN : transfer complete interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

HINTEN : half transfer interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

EINTEN : transfer error interrupt enable
bits : 3 - 3 (1 bit)
access : read-write

DIR : data transfer direction
bits : 4 - 4 (1 bit)
access : read-write

CIR : circular mode
bits : 5 - 5 (1 bit)
access : read-write

PERIINC : peripheral increment mode
bits : 6 - 6 (1 bit)
access : read-write

MEMINC : memory increment mode
bits : 7 - 7 (1 bit)
access : read-write

PERISZ : peripheral size
bits : 8 - 9 (2 bit)
access : read-write

MSZ : memory size
bits : 10 - 11 (2 bit)
access : read-write

PRI : channel priority level
bits : 12 - 13 (2 bit)
access : read-write

M2M : memory to memory mode
bits : 14 - 14 (1 bit)
access : read-write


LEN4

channel 4 transfer length
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LEN4 LEN4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEN

LEN : channel 4 number of data to transfer
bits : 0 - 15 (16 bit)
access : read-write


PERIADDR4

channel 4 peripheral address
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERIADDR4 PERIADDR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : channel 4 peripheral address
bits : 0 - 31 (32 bit)
access : read-write


MEMADDR4

channel 4 memory address
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMADDR4 MEMADDR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : channel 4 memory address
bits : 0 - 31 (32 bit)
access : read-write


CFG5

channel 5 channel configuration
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG5 CFG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN CINTEN HINTEN EINTEN DIR CIR PERIINC MEMINC PERISZ MSZ PRI M2M

CHEN : channel enable
bits : 0 - 0 (1 bit)
access : read-write

CINTEN : transfer complete interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

HINTEN : half transfer interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

EINTEN : transfer error interrupt enable
bits : 3 - 3 (1 bit)
access : read-write

DIR : data transfer direction
bits : 4 - 4 (1 bit)
access : read-write

CIR : circular mode
bits : 5 - 5 (1 bit)
access : read-write

PERIINC : peripheral increment mode
bits : 6 - 6 (1 bit)
access : read-write

MEMINC : memory increment mode
bits : 7 - 7 (1 bit)
access : read-write

PERISZ : peripheral size
bits : 8 - 9 (2 bit)
access : read-write

MSZ : memory size
bits : 10 - 11 (2 bit)
access : read-write

PRI : channel priority level
bits : 12 - 13 (2 bit)
access : read-write

M2M : memory to memory mode
bits : 14 - 14 (1 bit)
access : read-write


LEN5

channel 5 transfer length
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LEN5 LEN5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEN

LEN : channel 5 number of data to transfer
bits : 0 - 15 (16 bit)
access : read-write


PERIADDR5

channel 5 peripheral address
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERIADDR5 PERIADDR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : channel 5 peripheral address
bits : 0 - 31 (32 bit)
access : read-write


MEMADDR5

channel 5 memory address
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMADDR5 MEMADDR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : channel 5 memory address
bits : 0 - 31 (32 bit)
access : read-write


CFG1

channel 1 channel configuration
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG1 CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN CINTEN HINTEN EINTEN DIR CIR PERIINC MEMINC PERISZ MSZ PRI M2M

CHEN : channel enable
bits : 0 - 0 (1 bit)
access : read-write

CINTEN : transfer complete interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

HINTEN : half transfer interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

EINTEN : transfer error interrupt enable
bits : 3 - 3 (1 bit)
access : read-write

DIR : data transfer direction
bits : 4 - 4 (1 bit)
access : read-write

CIR : circular mode
bits : 5 - 5 (1 bit)
access : read-write

PERIINC : peripheral increment mode
bits : 6 - 6 (1 bit)
access : read-write

MEMINC : memory increment mode
bits : 7 - 7 (1 bit)
access : read-write

PERISZ : peripheral size
bits : 8 - 9 (2 bit)
access : read-write

MSZ : memory size
bits : 10 - 11 (2 bit)
access : read-write

PRI : channel priority level
bits : 12 - 13 (2 bit)
access : read-write

M2M : memory to memory mode
bits : 14 - 14 (1 bit)
access : read-write


LEN1

channel 1 transfer length
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LEN1 LEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEN

LEN : channel 1 number of data to transfer
bits : 0 - 15 (16 bit)
access : read-write



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