\n

EFC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CFG

CTL

ADDR

OPTBSTAT

WPROTSTAT

CTLKEY

OPTBKEY

STAT


CFG

EFC configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITCYCLE PRFEN PRFSTAT

WAITCYCLE : The value of this bit specifies if extra wait-state is necessary to read the eflash.
bits : 0 - 2 (3 bit)
access : read-write

PRFEN : This bit enables the prefetch
bits : 4 - 4 (1 bit)
access : read-write

PRFSTAT : Prefetch buffer status 0: not Prefetch 1: Prefetch has occurred
bits : 5 - 5 (1 bit)
access : read-only


CTL

EFC control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRG PER MER OPTBPRG OPTBER START LOCK OPTBWEN ERRINTEN ENDINTEN OPTBLDEN

PRG : eflash programming chosen 0: not chose main memory program operation 1: chose main memory program operation
bits : 0 - 0 (1 bit)
access : read-write

PER : Page erase chosen 0: not chose main memory page erase operation 1: chose main memory page erase operation
bits : 1 - 1 (1 bit)
access : read-write

MER : Mass erase chosen 0: not chose main memory mass erase operation 1: chose main memory mass erase operation
bits : 2 - 2 (1 bit)
access : read-write

OPTBPRG : Option byte programming chosen 0: not chose option bytes program operation 1: chose option bytes program operation
bits : 4 - 4 (1 bit)
access : read-write

OPTBER : Option byte erase chosen 0: not chose option bytes erase operation 1: chose option bytes erase operation
bits : 5 - 5 (1 bit)
access : read-write

START : This bit triggers an erase operation when set. This bit is set only by software and reset when the BSY bit is reset
bits : 6 - 6 (1 bit)
access : read-write

LOCK : Write to 1 only. When it is set, it indicates that the EFC_CTL is locked. This bit is reset by hardware after detecting the unlock sequence. In the event of unsuccessful unlock operation
bits : 7 - 7 (1 bit)
access : read-write

OPTBWEN : When set, the option byte can be programmed. This bit is set on writing the correct key sequence to the EFC_OPTBKEY register. This bit can be reset by software
bits : 9 - 9 (1 bit)
access : read-write

ERRINTEN : Error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

ENDINTEN : End of operation interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

OPTBLDEN : Setting this bit, the software requests the reloading of Option byte and generate a system reset.
bits : 13 - 13 (1 bit)
access : read-write


ADDR

page address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Set by software to indicate the chosen page to erase
bits : 0 - 31 (32 bit)
access : read-write


OPTBSTAT

option bytes status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OPTBSTAT OPTBSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPTBERR PROTLVL SWFWDT nRSTSTP nRSTSTB nBOOT1 VDDAMONTR SRAMPRTYCHK DATA0 DATA1

OPTBERR : Option byte error 0: not option bytes mismatch error 1: option bytes mismatch error occurred
bits : 0 - 0 (1 bit)
access : read-only

PROTLVL : Read protection level status 00: Read protection level 0 is enabled 01: Read protection level 1 is enabled 11: Read protection level 2 is enabled
bits : 1 - 2 (2 bit)
access : read-only

SWFWDT : Software watchdog selection 0: Hardware watchdog 1: Software watchdog
bits : 8 - 8 (1 bit)
access : read-only

nRSTSTP : Power management reset chosen when enter stop mode 0: Reset generated when entering Stop mode 1: No reset generated
bits : 9 - 9 (1 bit)
access : read-only

nRSTSTB : Power management reset chosen when enter standby mode 0: Reset generated when entering Standby mode. 1: No reset generated.
bits : 10 - 10 (1 bit)
access : read-only

nBOOT1 : Together with the BOOT0 signal, it selects the device boot mode
bits : 12 - 12 (1 bit)
access : read-only

VDDAMONTR : VDDA power supply supervisor selection 0: VDDA power supply supervisor disabled 1: VDDA power supply supervisor enabled
bits : 13 - 13 (1 bit)
access : read-only

SRAMPRTYCHK : RAM parity check selection 0: RAM parity check enabled 1: RAM parity check disabled
bits : 14 - 14 (1 bit)
access : read-only

DATA0 : User data byte 0
bits : 16 - 23 (8 bit)
access : read-only

DATA1 : User data byte 1
bits : 24 - 31 (8 bit)
access : read-only


WPROTSTAT

write protect status register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPROTSTAT WPROTSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPROT

WPROT : Write protection
bits : 0 - 7 (8 bit)
access : read-only


CTLKEY

Control register key
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CTLKEY CTLKEY write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTLKEY

CTLKEY : Control register key With a sequence of two write operations (the first one with 0x45670123 and the second one with 0xCDEF89AB), it is possible to unlock the EFC_CTL register.
bits : 0 - 31 (32 bit)
access : write-only


OPTBKEY

OPTBWEN bit key
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OPTBKEY OPTBKEY write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPTBKEY

OPTBKEY : OPTBWEN bit key With a sequence of two write operations (the first one with 0x45670123 and the second one with 0xCDEF89AB), it is possible to unlock the OPTBWEN bit.
bits : 0 - 31 (32 bit)
access : write-only


STAT

EFC status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BSY PRGERR WPROTERR ENDF

BSY : Operation in progress flag 0: no operation is in progress 1: erase/program operation is in progress
bits : 0 - 0 (1 bit)
access : read-only

PRGERR : Set by hardware when an address to be programed is not an erased value 0: no program error 1: program error occurred
bits : 2 - 2 (1 bit)
access : read-write

WPROTERR : Set by hardware when an address to be programmed or erased is write-protected. 0: no write-protected error 1: write-protected error occurred
bits : 4 - 4 (1 bit)
access : read-write

ENDF : End of program/erase 0: not end of program/erase 1: end of program/erase has occurred
bits : 5 - 5 (1 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.