\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
i2c control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2CEN : I2C enable
bits : 0 - 0 (1 bit)
access : read-write
TXINTEN : TX interrupt enable
bits : 1 - 1 (1 bit)
access : read-write
RXINTEN : RX interrupt enable
bits : 2 - 2 (1 bit)
access : read-write
ADDRINTEN : Address match interrupt enable(slave only)
bits : 3 - 3 (1 bit)
access : read-write
NACKINTEN : Not acknowledge received interrupt enable
bits : 4 - 4 (1 bit)
access : read-write
STOPINTEN : STOP detection interrupt enable
bits : 5 - 5 (1 bit)
access : read-write
TCINTEN : Transfer complete interrupt enable
bits : 6 - 6 (1 bit)
access : read-write
ERRINTEN : Error interrupts enable
bits : 7 - 7 (1 bit)
access : read-write
DNFCFG : Digital noise filter configuration
bits : 8 - 11 (4 bit)
access : read-write
ANFDIS : Analog noise filter disable
bits : 12 - 12 (1 bit)
access : read-write
DMATXEN : DMA transmission requests enable
bits : 14 - 14 (1 bit)
access : read-write
DMARXEN : DMA reception requests enable
bits : 15 - 15 (1 bit)
access : read-write
SBCTL : Slave byte control
bits : 16 - 16 (1 bit)
access : read-write
CLKSTHDIS : Clock stretching disable
bits : 17 - 17 (1 bit)
access : read-write
WAKEUPEN : Wakeup from stop mode enable
bits : 18 - 18 (1 bit)
access : read-write
GCEN : General call enable
bits : 19 - 19 (1 bit)
access : read-write
SMBHADDREN : SMBus Host address enable
bits : 20 - 20 (1 bit)
access : read-write
SMBDADDREN : SMBus device default address enable
bits : 21 - 21 (1 bit)
access : read-write
SMBALTEN : SMBus alert enable
bits : 22 - 22 (1 bit)
access : read-write
PECEN : PEC enable
bits : 23 - 23 (1 bit)
access : read-write
I2C timing configuration
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCLLPRD : SCL low period (master mode)
bits : 0 - 7 (8 bit)
access : read-write
SCLHPRD : SCL high period (master mode)
bits : 8 - 15 (8 bit)
access : read-write
SDADEL : Data hold time
bits : 16 - 19 (4 bit)
access : read-write
SCLDEL : Data setup time
bits : 20 - 23 (4 bit)
access : read-write
DIV : I2C CLK divider
bits : 28 - 31 (4 bit)
access : read-write
SMBUS timeout configuration
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TO : Bus Timeout
bits : 0 - 11 (12 bit)
access : read-write
IDLETOEN : Idle clock timeout detection
bits : 12 - 12 (1 bit)
access : read-write
TOEN : Clock timeout enable
bits : 15 - 15 (1 bit)
access : read-write
EXTTO : Extend clock timeout
bits : 16 - 27 (12 bit)
access : read-write
EXTTOEN : Extended clock timeout enable
bits : 31 - 31 (1 bit)
access : read-write
i2c interrupt and states
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXEF : Transmit data register empty flag (transmitters)
bits : 0 - 0 (1 bit)
access : read-write
TXINTSTAT : Transmit interrupt status (transmitters)
bits : 1 - 1 (1 bit)
access : read-write
RXNEF : Receive data register not empty flag (receivers)
bits : 2 - 2 (1 bit)
access : read-only
ADDRF : Address matched flag (slave mode)
bits : 3 - 3 (1 bit)
access : read-only
NACKF : Not Acknowledge received flag
bits : 4 - 4 (1 bit)
access : read-only
STOPF : Stop detection flag
bits : 5 - 5 (1 bit)
access : read-only
TCF : Transfer Complete flag (master mode)
bits : 6 - 6 (1 bit)
access : read-only
TCRF : Transfer Complete Reload flag
bits : 7 - 7 (1 bit)
access : read-only
BERRF : Bus error flag
bits : 8 - 8 (1 bit)
access : read-only
ARLOF : Arbitration lost flag
bits : 9 - 9 (1 bit)
access : read-only
OVRF : Overrun/Underrun flag (slave mode)
bits : 10 - 10 (1 bit)
access : read-only
PECERRF : PEC Error in reception flag
bits : 11 - 11 (1 bit)
access : read-only
SMBTOF : Timeout or tLOW detection flag
bits : 12 - 12 (1 bit)
access : read-only
SMBALTF : SMBus alert flag
bits : 13 - 13 (1 bit)
access : read-only
BSYF : Bus busy flag
bits : 15 - 15 (1 bit)
access : read-only
TRANSDIR : Transfer direction (Slave mode)
bits : 16 - 16 (1 bit)
access : read-only
RECADDR : Received address (Slave mode)
bits : 17 - 23 (7 bit)
access : read-only
i2c interrupt flag clear
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ADDRFCLR : Address matched flag clear
bits : 3 - 3 (1 bit)
access : write-only
NACKFCLR : Not Acknowledge flag clear
bits : 4 - 4 (1 bit)
access : write-only
STOPFCLR : Stop detection flag clear
bits : 5 - 5 (1 bit)
access : write-only
BERRFCLR : Bus error flag clear
bits : 8 - 8 (1 bit)
access : write-only
ARLOFCLR : Arbitration Lost flag clear
bits : 9 - 9 (1 bit)
access : write-only
OVRFCLR : Overrun/Underrun flag clear
bits : 10 - 10 (1 bit)
access : write-only
PECERRFCLR : PEC Error flag clear
bits : 11 - 11 (1 bit)
access : write-only
SMBTOFCLR : SMBUS timeout detection flag clear
bits : 12 - 12 (1 bit)
access : write-only
SMBALTFCLR : SMBUS alert flag clear
bits : 13 - 13 (1 bit)
access : write-only
Packet error checking data
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PECDATA : Packet error checking data
bits : 0 - 7 (8 bit)
access : read-only
8-bit receive data
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : 8-bit receive data Data byte received from the I2C bus
bits : 0 - 7 (8 bit)
access : read-only
8-bit transmit data
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDATA : 8-bit transmit data
bits : 0 - 7 (8 bit)
access : read-write
i2c control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Slave address bit
bits : 0 - 9 (10 bit)
access : read-write
TRANSDIR : Transfer direction (master mode)
bits : 10 - 10 (1 bit)
access : read-write
ADDRMOD : Addressing mode (master mode)
bits : 11 - 11 (1 bit)
access : read-write
HEAD10REN : 10-bit address header only read direction enable (master receiver mode)
bits : 12 - 12 (1 bit)
access : read-write
STARTGEN : Start generation
bits : 13 - 13 (1 bit)
access : read-write
STOPGEN : Stop generation (master mode)
bits : 14 - 14 (1 bit)
access : read-write
NACKGEN : NACK generation (slave mode)
bits : 15 - 15 (1 bit)
access : read-write
LEN : Length of bytes
bits : 16 - 23 (8 bit)
access : read-write
RLDEN : Reload enable
bits : 24 - 24 (1 bit)
access : read-write
AUTOSTOPEN : Automatic stop mode enable (master mode)
bits : 25 - 25 (1 bit)
access : read-write
PECTRANS : Packet error checking transfer
bits : 26 - 26 (1 bit)
access : read-write
Device address 0 configuration
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR0 : Device address 0
bits : 0 - 9 (10 bit)
access : read-write
DADDR0MOD : Device Address 0 10-bit mode
bits : 10 - 10 (1 bit)
access : read-write
DADDR0EN : Device Address 0 enable
bits : 15 - 15 (1 bit)
access : read-write
Device address 1 configuration
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR1 : Device address 1
bits : 1 - 7 (7 bit)
access : read-write
DADDR1MSK : Device address 1 masks
bits : 8 - 10 (3 bit)
access : read-write
DADDR1EN : Device address 1 enable
bits : 15 - 15 (1 bit)
access : read-write
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