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PMU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTL

STAT


CTL

PMU Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RGLP STBEN CLRWUF CLRSTBF DISPROT

RGLP : Regulator in Low-power deep-sleep mode
bits : 0 - 0 (1 bit)
access : read-write

STBEN : Standby enable
bits : 1 - 1 (1 bit)
access : read-write

CLRWUF : Clear wakeup flag
bits : 2 - 2 (1 bit)
access : read-write

CLRSTBF : Clear standby flag
bits : 3 - 3 (1 bit)
access : read-write

DISPROT : Disable RTC write protection
bits : 8 - 8 (1 bit)
access : read-write


STAT

PMU State Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUF STBF WU0EN WU1EN

WUF : Wakeup flag
bits : 0 - 0 (1 bit)
access : read-only

STBF : Standby flag
bits : 1 - 1 (1 bit)
access : read-only

WU0EN : Enable WKUP pin 0
bits : 8 - 8 (1 bit)
access : read-write

WU1EN : Enable WKUP pin 1
bits : 9 - 9 (1 bit)
access : read-write



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