\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
RCC control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC8MEN : RC8M clock enable
bits : 0 - 0 (1 bit)
access : read-write
RC8MRDY : RC8M clock ready flag
bits : 1 - 1 (1 bit)
access : read-only
RC8MTRIM : RC8M clock trim
bits : 3 - 7 (5 bit)
access : read-write
RC8MCAL : RC8M calibration data which are saved in flash
bits : 8 - 15 (8 bit)
access : read-only
HXOSCEN : HXOSC clock ready flag
bits : 16 - 16 (1 bit)
access : read-write
HXOSCRDY : HXOSC clock ready flag
bits : 17 - 17 (1 bit)
access : read-only
HXOSCBYP : HXOSC clock BYPASS enable
bits : 18 - 18 (1 bit)
access : read-write
CLKSECEN : clock security system enable
bits : 19 - 19 (1 bit)
access : read-write
PLLEN : PLL clock enable
bits : 24 - 24 (1 bit)
access : read-write
APB peripheral reset register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMERG1RST : TIMERG1 reset
bits : 1 - 1 (1 bit)
access : read-write
TIMERG2RST : TIMERG2 reset
bits : 8 - 8 (1 bit)
access : read-write
WWDTRST : WWDT reset
bits : 11 - 11 (1 bit)
access : read-write
I2C1RST : I2C1 reset
bits : 21 - 21 (1 bit)
access : read-write
PMURST : PMU reset
bits : 28 - 28 (1 bit)
access : read-write
AHB peripheral clock enable
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : DMA clock enable
bits : 0 - 0 (1 bit)
access : read-write
SRAMEN : SRAM clock enable
bits : 2 - 2 (1 bit)
access : read-write
EFCEN : FLASH clock enable
bits : 4 - 4 (1 bit)
access : read-write
CRCEN : CRC clock enable
bits : 6 - 6 (1 bit)
access : read-write
GPIOAEN : GPIO PORT A clock enable
bits : 17 - 17 (1 bit)
access : read-write
GPIOBEN : GPIO PORT B clock enable
bits : 18 - 18 (1 bit)
access : read-write
GPIOCEN : GPIO PORT C clock enable
bits : 19 - 19 (1 bit)
access : read-write
GPIOFEN : GPIO PORT F clock enable
bits : 22 - 22 (1 bit)
access : read-write
APB peripheral clock enable 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCFGEN : SYSCFG clock enable
bits : 0 - 0 (1 bit)
access : read-write
ADCEN : ADC clock enable
bits : 9 - 9 (1 bit)
access : read-write
TIMERA1EN : TIMERA1 clock enable
bits : 11 - 11 (1 bit)
access : read-write
SPI1EN : SPI1 clock enable
bits : 12 - 12 (1 bit)
access : read-write
USART1EN : USART1 clock enable
bits : 14 - 14 (1 bit)
access : read-write
TIMERG3EN : TIMERG3 clock enable
bits : 17 - 17 (1 bit)
access : read-write
TIMERG4EN : TIMERG4 clock enable
bits : 18 - 18 (1 bit)
access : read-write
DBGEN : DBG clock enable
bits : 22 - 22 (1 bit)
access : read-write
APB peripheral clock enable 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMERG1EN : TIMERG1 clock enable
bits : 1 - 1 (1 bit)
access : read-write
TIMERG2EN : TIMERG2 clock enable
bits : 8 - 8 (1 bit)
access : read-write
WWDTEN : WWDT clock enable
bits : 11 - 11 (1 bit)
access : read-write
I2C1EN : I2C1 clock enable
bits : 21 - 21 (1 bit)
access : read-write
PMUEN : PMU clock enable
bits : 28 - 28 (1 bit)
access : read-write
RCC RTC domain control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LXOSCEN : LXOSC clock enable
bits : 0 - 0 (1 bit)
access : read-write
LXOSCRDY : LXOSC clock enable
bits : 1 - 1 (1 bit)
access : read-only
LXOSCBYP : LXOSC clock bypass enable
bits : 2 - 2 (1 bit)
access : read-write
LXOSCDRV : LXOSC clock drive capability
bits : 3 - 4 (2 bit)
access : read-write
RTCSRCSEL : RTC clock source
bits : 8 - 9 (2 bit)
access : read-write
RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write
RTCRST : RTC domain software reset
bits : 16 - 16 (1 bit)
access : read-write
RCC status register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC40KEN : RC40K enable
bits : 0 - 0 (1 bit)
access : read-write
RC40KRDY : LXOSC clock enable
bits : 1 - 1 (1 bit)
access : read-only
TSCCLKEN : touch clock enable if touch exist , this bit shall enable the clocks of both ADC and touch otherwise, this bit is inaccessible
bits : 16 - 16 (1 bit)
access : read-write
PMURSTF : VDD for core power up flag, including POWER ON and STDBY EXIT
bits : 23 - 23 (1 bit)
access : read-only
CLRRSTF : remove reset flag
bits : 24 - 24 (1 bit)
access : write-only
OPTBLDENRSTF : option byte load reset flag
bits : 25 - 25 (1 bit)
access : read-only
EXPINRSTF : pin reset flag
bits : 26 - 26 (1 bit)
access : read-only
PORRSTF : POR reset flag
bits : 27 - 27 (1 bit)
access : read-only
SFTRSTF : CPU software reset flag
bits : 28 - 28 (1 bit)
access : read-only
FWDTRSTF : FWDT reset flag
bits : 29 - 29 (1 bit)
access : read-only
WWDTRSTF : WWDT reset flag
bits : 30 - 30 (1 bit)
access : read-only
LPWRRSTF : low power management reset flag
bits : 31 - 31 (1 bit)
access : read-only
AHB peripheral reset
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOARST : GPIO PORT A reset
bits : 17 - 17 (1 bit)
access : read-write
GPIOBRST : GPIO PORT B reset
bits : 18 - 18 (1 bit)
access : read-write
GPIOCRST : GPIO PORT C reset
bits : 19 - 19 (1 bit)
access : read-write
GPIOFRST : GPIO PORT F reset
bits : 22 - 22 (1 bit)
access : read-write
TSCRST : touch reset if touch exist , this bit shall reset both ADC and touch otherwise, this bit is inaccessible
bits : 31 - 31 (1 bit)
access : read-write
RCC configuration register 1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLPDIV : PLL division factor
bits : 0 - 3 (4 bit)
access : read-write
RCC configuration register 2
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USART1SEL : USART1 clock source
bits : 0 - 1 (2 bit)
access : read-write
I2C1SEL : I2C1 clock source
bits : 4 - 4 (1 bit)
access : read-write
RCC control register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC14MEN : RC14M clock enable
bits : 0 - 0 (1 bit)
access : read-write
RC14MRDY : RC14M clock stable
bits : 1 - 1 (1 bit)
access : read-only
RC14MDISADC : disable ADC request for RC14M clock
bits : 2 - 2 (1 bit)
access : read-write
RC14MTRIM : RC14M clock trimming, which is added to ro_RC14M_cal
bits : 3 - 7 (5 bit)
access : read-write
RC14MCAL : RC14M clock calibration
bits : 8 - 15 (8 bit)
access : read-only
RCC configuration register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCLKSW : system clock source
bits : 0 - 1 (2 bit)
access : read-write
SYSCLKSTAT : system clock source status
bits : 2 - 3 (2 bit)
access : read-only
AHBPDIV : AHB clock prescale
bits : 4 - 7 (4 bit)
access : read-write
APBPDIV : APB clock prescale
bits : 8 - 10 (3 bit)
access : read-write
PLLSRCCLK : PLL CLOCK SOURCE
bits : 16 - 16 (1 bit)
access : read-write
PLLHXOSCPDIV : HXOSC clock div for PLL
bits : 17 - 17 (1 bit)
access : read-write
PLLMULT : PLL multiplication factor
bits : 18 - 21 (4 bit)
access : read-write
CLKO : microcontroller clock output
bits : 24 - 27 (4 bit)
access : read-write
CLKOPDIV : microcontroller clock output prescale
bits : 28 - 30 (3 bit)
access : read-write
PLLDIVCLKO : PLL clock not divided for MCO
bits : 31 - 31 (1 bit)
access : read-write
RCC interrupt control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC40KRDYF : RC40K ready interrupt flag
bits : 0 - 0 (1 bit)
access : read-only
LXOSCRDYF : LXOSC ready interrupt flag
bits : 1 - 1 (1 bit)
access : read-only
RC8MRDYF : RC8M ready interrupt flag
bits : 2 - 2 (1 bit)
access : read-only
HXOSCRDYF : HXOSC ready interrupt flag
bits : 3 - 3 (1 bit)
access : read-only
RC14MRDYF : RC14M ready interrupt flag
bits : 5 - 5 (1 bit)
access : read-only
CLKSECF : CSSHXOSC interrupt flag
bits : 7 - 7 (1 bit)
access : read-only
RC40KRDYINTEN : RC40K interrupt flag enable
bits : 8 - 8 (1 bit)
access : read-write
LXOSCRDYINTEN : LXOSC ready interrupt flag enable
bits : 9 - 9 (1 bit)
access : read-write
RC8MRDYINTEN : RC8M ready interrupt flag enable
bits : 10 - 10 (1 bit)
access : read-write
HXOSCRDYINTEN : HXOSC ready interrupt flag enable
bits : 11 - 11 (1 bit)
access : read-write
RC14MRDYINTEN : RC14M ready interrupt flag enable
bits : 13 - 13 (1 bit)
access : read-write
RC40KRDYCLR : RC40K ready interrupt flag clear
bits : 16 - 16 (1 bit)
access : write-only
LXOSCRDYCLR : LXOSC ready interrupt flag clear
bits : 17 - 17 (1 bit)
access : write-only
RC8MRDYCLR : RC8M ready interrupt flag clear
bits : 18 - 18 (1 bit)
access : write-only
HXOSCRDYCLR : HXOSC ready interrupt flag clear
bits : 19 - 19 (1 bit)
access : write-only
RC14MRDYCLR : RC14M ready interrupt flag clear
bits : 21 - 21 (1 bit)
access : write-only
CLKSECCLR : CLKSEC interrupt flag clear
bits : 23 - 23 (1 bit)
access : write-only
APB peripheral reset register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCFGRST : SYSCFG reset
bits : 0 - 0 (1 bit)
access : read-write
ADCRST : ADC reset
bits : 9 - 9 (1 bit)
access : read-write
TIMERA1RST : TIMERA1 reset
bits : 11 - 11 (1 bit)
access : read-write
SPI1RST : SPI1 reset
bits : 12 - 12 (1 bit)
access : read-write
USART1RST : USART1 reset
bits : 14 - 14 (1 bit)
access : read-write
TIMERG3RST : TIMERG3 reset
bits : 17 - 17 (1 bit)
access : read-write
TIMERG4RST : TIMERG4 reset
bits : 18 - 18 (1 bit)
access : read-write
DBGRST : debug register reset
bits : 22 - 22 (1 bit)
access : read-write
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