\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
SPI control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPHA : Clock phase
bits : 0 - 0 (1 bit)
access : read-write
CPOL : Clock polarity
bits : 1 - 1 (1 bit)
access : read-write
MASTER : Master selection
bits : 2 - 2 (1 bit)
access : read-write
BRDIV : Baud rate control
bits : 3 - 5 (3 bit)
access : read-write
SPIEN : SPI enable
bits : 6 - 6 (1 bit)
access : read-write
LSBFIRST : Frame format
bits : 7 - 7 (1 bit)
access : read-write
INCS : Internal slave select
bits : 8 - 8 (1 bit)
access : read-write
SWCS : Software slave management
bits : 9 - 9 (1 bit)
access : read-write
SDUPDIR : Receive only mode enable
bits : 10 - 10 (1 bit)
access : read-write
CRCLEN : CRC length
bits : 11 - 11 (1 bit)
access : read-write
CRCTRIG : CRC transfer next
bits : 12 - 12 (1 bit)
access : read-write
CRCEN : Hardware CRC calculation enable
bits : 13 - 13 (1 bit)
access : read-write
HFDUPDIR : Output enable in bidirectional mode
bits : 14 - 14 (1 bit)
access : read-write
HFDUPEN : Bidirectional data mode enable
bits : 15 - 15 (1 bit)
access : read-write
SPI CRC polynomial register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRCPOL : CRC polynomial
bits : 0 - 15 (16 bit)
access : read-write
SPI RX CRC register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXCRC : RX CRC register
bits : 0 - 15 (16 bit)
access : read-only
SPI TX CRC register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXCRC : TX CRC register
bits : 0 - 15 (16 bit)
access : read-only
I2S configuration register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHLEN : Channel length
bits : 0 - 0 (1 bit)
access : read-write
DATALEN : Data length to be transferred
bits : 1 - 2 (2 bit)
access : read-write
CLKPOL : Inactive state clock polarity
bits : 3 - 3 (1 bit)
access : read-write
I2SSTD : I2S standard selection
bits : 4 - 5 (2 bit)
access : read-write
PCMSYNC : PCM frame synchronization
bits : 7 - 7 (1 bit)
access : read-write
I2SCFG : I2S configuration mode
bits : 8 - 9 (2 bit)
access : read-write
I2SEN : I2S enable
bits : 10 - 10 (1 bit)
access : read-write
I2SMOD : I2S mode selection
bits : 11 - 11 (1 bit)
access : read-write
I2S prescale register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : I2S linear prescale
bits : 0 - 7 (8 bit)
access : read-write
ODD : Odd factor for the prescale
bits : 8 - 8 (1 bit)
access : read-write
MCLKEN : Master clock output enable
bits : 9 - 9 (1 bit)
access : read-write
SPI control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMARXEN : RX buffer DMA enable
bits : 0 - 0 (1 bit)
access : read-write
DMATXEN : TX buffer DMA enable
bits : 1 - 1 (1 bit)
access : read-write
CSOEN : SS output enable
bits : 2 - 2 (1 bit)
access : read-write
CSPEN : NSS pulse management
bits : 3 - 3 (1 bit)
access : read-write
TIMOD : Frame format
bits : 4 - 4 (1 bit)
access : read-write
ERRINTEN : Error interrupt enable
bits : 5 - 5 (1 bit)
access : read-write
RXNEINTEN : RX buffer not empty interrupt enable
bits : 6 - 6 (1 bit)
access : read-write
TXEINTEN : TX buffer empty interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
FRMLEN : Data size
bits : 8 - 11 (4 bit)
access : read-write
RXTH : FIFO reception threshold
bits : 12 - 12 (1 bit)
access : read-write
DMARXLB : Last DMA transfer for reception
bits : 13 - 13 (1 bit)
access : read-write
DMATXLB : Last DMA transfer for transmission
bits : 14 - 14 (1 bit)
access : read-write
SPI status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXNE : Receive buffer not empty
bits : 0 - 0 (1 bit)
access : read-only
TXE : Transmit buffer empty
bits : 1 - 1 (1 bit)
access : read-only
CHF : Channel side
bits : 2 - 2 (1 bit)
access : read-only
UDRF : Underrun flag
bits : 3 - 3 (1 bit)
access : read-only
CRCERRF : CRC error flag
bits : 4 - 4 (1 bit)
access : read-only
MODERRF : Mode fault
bits : 5 - 5 (1 bit)
access : read-only
OVRF : Overrun flag
bits : 6 - 6 (1 bit)
access : read-only
BSYF : Busy flag
bits : 7 - 7 (1 bit)
access : read-only
FRMERRF : Frame Error
bits : 8 - 8 (1 bit)
access : read-only
FRVOL : FIFO reception level
bits : 9 - 10 (2 bit)
access : read-only
FTVOL : FIFO Transmission Level
bits : 11 - 12 (2 bit)
access : read-only
SPI data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data register
bits : 0 - 15 (16 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.