\n

SYSCFG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CFG0

EXTISS2

EXTISS3

CFG1

EXTISS0

EXTISS1


CFG0

memory configuration, DMA request remap and I/O features control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG0 CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMMAPSEL ADCRMPDMA USART1TXRMPDMA USART1RXRMPDMA TIMERG3RMPDMA TIMERG4RMPDMA I2CFMPENPB6 I2CFMPENPB7 I2CFMPENPB8 I2CFMPENPB9 I2C1FMPEN I2CFMPENPA9 I2CFMPENPA10

MEMMAPSEL : memory mapping selection
bits : 0 - 1 (2 bit)
access : read-write

ADCRMPDMA : ADC DMA request remapping
bits : 8 - 8 (1 bit)
access : read-write

USART1TXRMPDMA : USART1 TX DMA request remapping
bits : 9 - 9 (1 bit)
access : read-write

USART1RXRMPDMA : USART1 RX DMA request remapping
bits : 10 - 10 (1 bit)
access : read-write

TIMERG3RMPDMA : TIMERG3 DMA request remapping
bits : 11 - 11 (1 bit)
access : read-write

TIMERG4RMPDMA : TIMERG4 DMA request remapping
bits : 12 - 12 (1 bit)
access : read-write

I2CFMPENPB6 : I2C PB6 FM+ driving capability activation
bits : 16 - 16 (1 bit)
access : read-write

I2CFMPENPB7 : I2C PB7 FM+ driving capability activation
bits : 17 - 17 (1 bit)
access : read-write

I2CFMPENPB8 : I2C PB8 FM+ driving capability activation
bits : 18 - 18 (1 bit)
access : read-write

I2CFMPENPB9 : I2C PB9 FM+ driving capability activation
bits : 19 - 19 (1 bit)
access : read-write

I2C1FMPEN : I2C1 FM+ driving capability activation
bits : 20 - 20 (1 bit)
access : read-write

I2CFMPENPA9 : I2C PA9 FM+ driving capability activation
bits : 22 - 22 (1 bit)
access : read-write

I2CFMPENPA10 : I2C PA10 FM+ driving capability activation
bits : 23 - 23 (1 bit)
access : read-write


EXTISS2

EXTI 8-11 source select
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTISS2 EXTISS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI8SS EXTI9SS EXTI10SS EXTI11SS

EXTI8SS : EXTI 8 source select
bits : 0 - 3 (4 bit)
access : read-write

EXTI9SS : EXTI 9 source select
bits : 4 - 7 (4 bit)
access : read-write

EXTI10SS : EXTI 10 source select
bits : 8 - 11 (4 bit)
access : read-write

EXTI11SS : EXTI 11 source select
bits : 12 - 15 (4 bit)
access : read-write


EXTISS3

EXTI 12-15 source select
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTISS3 EXTISS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI12SS EXTI13SS EXTI14SS EXTI15SS

EXTI12SS : EXTI 12 source select
bits : 0 - 3 (4 bit)
access : read-write

EXTI13SS : EXTI 13 source select
bits : 4 - 7 (4 bit)
access : read-write

EXTI14SS : EXTI 14 source select
bits : 8 - 11 (4 bit)
access : read-write

EXTI15SS : EXTI 15 source select
bits : 12 - 15 (4 bit)
access : read-write


CFG1

error signal route, error flag
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG1 CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKUPS SRAMPES SRAMPEF OPAMP1EN OPAMP2EN

LOCKUPS : Cortex-M0 LOCKUP signal route
bits : 0 - 0 (1 bit)
access : read-write

SRAMPES : SRAM parity error signal route
bits : 1 - 1 (1 bit)
access : read-write

SRAMPEF : SRAM parity error flag
bits : 8 - 8 (1 bit)
access : read-write

OPAMP1EN : OPAMP1 enable
bits : 16 - 16 (1 bit)
access : read-write

OPAMP2EN : OPAMP2 enable
bits : 17 - 17 (1 bit)
access : read-write


EXTISS0

EXTI 0-3 source select
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTISS0 EXTISS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0SS EXTI1SS EXTI2SS EXTI3SS

EXTI0SS : EXTI 0 source select
bits : 0 - 3 (4 bit)
access : read-write

EXTI1SS : EXTI 1 source select
bits : 4 - 7 (4 bit)
access : read-write

EXTI2SS : EXTI 2 source select
bits : 8 - 11 (4 bit)
access : read-write

EXTI3SS : EXTI 3 source select
bits : 12 - 15 (4 bit)
access : read-write


EXTISS1

EXTI 4-7 source select
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTISS1 EXTISS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI4SS EXTI5SS EXTI6SS EXTI7SS

EXTI4SS : EXTI 4 source select
bits : 0 - 3 (4 bit)
access : read-write

EXTI5SS : EXTI 5 source select
bits : 4 - 7 (4 bit)
access : read-write

EXTI6SS : EXTI 6 source select
bits : 8 - 11 (4 bit)
access : read-write

EXTI7SS : EXTI 7 source select
bits : 12 - 15 (4 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.