\n

TIMERA1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTL0

STAT

EVTSET

CCTL0_output

CCTL0_input

CCTL1_output

CCTL1_input

CCTL2

DATA

DIV

RLD

REPT

CCMP0

CCMP1

CCMP2

CTL1

CCMP3

PROTCFG

DMACFG

DMARMP

SLVMODCTL

INTDMAEN


CTL0

control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL0 CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN UDIS USRC SGLPLSMOD CNTDIR ALIGNMOD RLDPRLDEN CLKDIV

EN : Counter enable
bits : 0 - 0 (1 bit)
access : read-write

UDIS : Update disable
bits : 1 - 1 (1 bit)
access : read-write

USRC : Update source
bits : 2 - 2 (1 bit)
access : read-write

SGLPLSMOD : single pulse mode
bits : 3 - 3 (1 bit)
access : read-write

CNTDIR : count direction
bits : 4 - 4 (1 bit)
access : read-write

ALIGNMOD : align mode
bits : 5 - 6 (2 bit)
access : read-write

RLDPRLDEN : reload preload enable
bits : 7 - 7 (1 bit)
access : read-write

CLKDIV : clock division
bits : 8 - 9 (2 bit)
access : read-write


STAT

status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UF C0F C1F C2F C3F COMF TRIGIF BRKF OVC0F OVC1F OVC2F OVC3F

UF : update flag
bits : 0 - 0 (1 bit)
access : read-write

C0F : capture/compare 0 flag
bits : 1 - 1 (1 bit)
access : read-write

C1F : capture/compare 1 flag
bits : 2 - 2 (1 bit)
access : read-write

C2F : capture/compare 2 flag
bits : 3 - 3 (1 bit)
access : read-write

C3F : capture/compare 3 flag
bits : 4 - 4 (1 bit)
access : read-write

COMF : commutation flag
bits : 5 - 5 (1 bit)
access : read-write

TRIGIF : trigger input flag
bits : 6 - 6 (1 bit)
access : read-write

BRKF : break flag
bits : 7 - 7 (1 bit)
access : read-write

OVC0F : over capture 0 flag
bits : 9 - 9 (1 bit)
access : read-write

OVC1F : over capture 1 flag
bits : 10 - 10 (1 bit)
access : read-write

OVC2F : over capture 2 flag
bits : 11 - 11 (1 bit)
access : read-write

OVC3F : over capture 3 flag
bits : 12 - 12 (1 bit)
access : read-write


EVTSET

event set register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EVTSET EVTSET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPDATE C0 C1 C2 C3 COM TRIGI BRK

UPDATE : update event set
bits : 0 - 0 (1 bit)
access : write-only

C0 : capture/compare 0 event set
bits : 1 - 1 (1 bit)
access : write-only

C1 : capture/compare 1 event set
bits : 2 - 2 (1 bit)
access : write-only

C2 : capture/compare 2 event set
bits : 3 - 3 (1 bit)
access : write-only

C3 : capture/compare 3 event set
bits : 4 - 4 (1 bit)
access : write-only

COM : commutation event set
bits : 5 - 5 (1 bit)
access : write-only

TRIGI : trigger input event set
bits : 6 - 6 (1 bit)
access : write-only

BRK : break event set
bits : 7 - 7 (1 bit)
access : write-only


CCTL0_output

capture/compare control register 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL0_output CCTL0_output read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICS0SRC OCS0FMEN OCS0PRLDEN OCS0MOD OCS0CLR ICS1SRC OCS1FMEN OCS1PRLDEN OCS1MOD OCS1CLR

ICS0SRC : input capture signal 0 source
bits : 0 - 1 (2 bit)
access : read-write

OCS0FMEN : output compare signal 0 Fast Mode enable
bits : 2 - 2 (1 bit)
access : read-write

OCS0PRLDEN : output compare signal 0 preload enable
bits : 3 - 3 (1 bit)
access : read-write

OCS0MOD : output compare signal 0 mode
bits : 4 - 6 (3 bit)
access : read-write

OCS0CLR : output compare signal 0 clear
bits : 7 - 7 (1 bit)
access : read-write

ICS1SRC : input capture signal 1 source
bits : 8 - 9 (2 bit)
access : read-write

OCS1FMEN : output compare signal 1 Fast Mode enable
bits : 10 - 10 (1 bit)
access : read-write

OCS1PRLDEN : output compare signal 1 preload enable
bits : 11 - 11 (1 bit)
access : read-write

OCS1MOD : output compare signal 1 mode
bits : 12 - 14 (3 bit)
access : read-write

OCS1CLR : output compare signal 1 clear
bits : 15 - 15 (1 bit)
access : read-write


CCTL0_input

capture/compare control register 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCTL0_output
reset_Mask : 0x0

CCTL0_input CCTL0_input read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICS0SRC ICS0DIV ICS0FLT ICS1SRC ICS1DIV ICS1FLT

ICS0SRC : input capture signal 0 source
bits : 0 - 1 (2 bit)
access : read-write

ICS0DIV : input capture signal 0 division
bits : 2 - 3 (2 bit)
access : read-write

ICS0FLT : input capture signal 0 filter
bits : 4 - 7 (4 bit)
access : read-write

ICS1SRC : input capture signal 1 source
bits : 8 - 9 (2 bit)
access : read-write

ICS1DIV : input capture signal 1 division
bits : 10 - 11 (2 bit)
access : read-write

ICS1FLT : input capture signal 1 filter
bits : 12 - 15 (4 bit)
access : read-write


CCTL1_output

capture/compare control register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL1_output CCTL1_output read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICS2SRC OCS2FMEN OCS2PRLDEN OCS2MOD OCS2CLR ICS3SRC OCS3FMEN OCS3PRLDEN OCS3MOD OCS3CLR

ICS2SRC : input capture signal 2 source
bits : 0 - 1 (2 bit)
access : read-write

OCS2FMEN : output compare signal 2 Fast mode enable
bits : 2 - 2 (1 bit)
access : read-write

OCS2PRLDEN : output compare signal2 preload enable
bits : 3 - 3 (1 bit)
access : read-write

OCS2MOD : output compare signal 2 mode
bits : 4 - 6 (3 bit)
access : read-write

OCS2CLR : output compare signal 2 clear
bits : 7 - 7 (1 bit)
access : read-write

ICS3SRC : input capture signal 3 source
bits : 8 - 9 (2 bit)
access : read-write

OCS3FMEN : output compare signal 3 Fast Mode enable
bits : 10 - 10 (1 bit)
access : read-write

OCS3PRLDEN : output compare signal 3 preload enable
bits : 11 - 11 (1 bit)
access : read-write

OCS3MOD : output compare signal 3 mode
bits : 12 - 14 (3 bit)
access : read-write

OCS3CLR : output compare signal 3 clear
bits : 15 - 15 (1 bit)
access : read-write


CCTL1_input

capture/compare control register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCTL1_output
reset_Mask : 0x0

CCTL1_input CCTL1_input read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICS2SRC ICS2DIV ICS2FLT ICS3SRC ICS3DIV ICS3FLT

ICS2SRC : input capture signal 2 source
bits : 0 - 1 (2 bit)
access : read-write

ICS2DIV : input capture signal 2 division
bits : 2 - 3 (2 bit)
access : read-write

ICS2FLT : input capture signal 2 filter
bits : 4 - 7 (4 bit)
access : read-write

ICS3SRC : input capture signal 3 source
bits : 8 - 9 (2 bit)
access : read-write

ICS3DIV : input capture signal 3division
bits : 10 - 11 (2 bit)
access : read-write

ICS3FLT : input capture signal 3 filter
bits : 12 - 15 (4 bit)
access : read-write


CCTL2

capture/compare control register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL2 CCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CS0EN CS0POL CS0REN CS0RPOL CS1EN CS1POL CS1REN CS1RPOL CS2EN CS2POL CS2REN CS2RPOL CS3EN CS3POL CS3RPOL

CS0EN : capture/compare signal 0 enable
bits : 0 - 0 (1 bit)
access : read-write

CS0POL : capture/compare signal 0 polarity level
bits : 1 - 1 (1 bit)
access : read-write

CS0REN : capture/compare signal 0 reverse enable
bits : 2 - 2 (1 bit)
access : read-write

CS0RPOL : capture/compare signal 0 reverse polarity level
bits : 3 - 3 (1 bit)
access : read-write

CS1EN : capture/compare signal 1 enable
bits : 4 - 4 (1 bit)
access : read-write

CS1POL : capture/compare signal 1 polarity level
bits : 5 - 5 (1 bit)
access : read-write

CS1REN : capture/compare signal 1 reverse enable
bits : 6 - 6 (1 bit)
access : read-write

CS1RPOL : capture/compare signal 1 reverse polarity level
bits : 7 - 7 (1 bit)
access : read-write

CS2EN : capture/compare signal 2 enable
bits : 8 - 8 (1 bit)
access : read-write

CS2POL : capture/compare signal 2 polarity level
bits : 9 - 9 (1 bit)
access : read-write

CS2REN : capture/compare signal 2 reverse enable
bits : 10 - 10 (1 bit)
access : read-write

CS2RPOL : capture/compare signal 2 reverse polarity level
bits : 11 - 11 (1 bit)
access : read-write

CS3EN : capture/compare signal 3 enable
bits : 12 - 12 (1 bit)
access : read-write

CS3POL : capture/compare signal 3 polarity level
bits : 13 - 13 (1 bit)
access : read-write

CS3RPOL : capture/compare signal 3 reverse polarity level
bits : 15 - 15 (1 bit)
access : read-write


DATA

timer' current data
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : timer data
bits : 0 - 15 (16 bit)
access : read-write


DIV

timer' divisions
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : timer divisions
bits : 0 - 15 (16 bit)
access : read-write


RLD

timer' reload
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RLD RLD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLD

RLD : timer reload
bits : 0 - 15 (16 bit)
access : read-write


REPT

timer' repetitions
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REPT REPT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REPT

REPT : timer repetitions
bits : 0 - 7 (8 bit)
access : read-write


CCMP0

capture/compare counter value 0
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCMP0 CCMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCMP0

CCMP0 : capture/compare counter value 0
bits : 0 - 15 (16 bit)
access : read-write


CCMP1

capture/compare counter value 1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCMP1 CCMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCMP1

CCMP1 : capture/compare counter value 1
bits : 0 - 15 (16 bit)
access : read-write


CCMP2

capture/compare counter value 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCMP2 CCMP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCMP2

CCMP2 : capture/compare counter value 2
bits : 0 - 15 (16 bit)
access : read-write


CTL1

control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL1 CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCPRLDEN CUSRC OCDMASRC TRIGOSRC IS0SRC OC0IDLSTAT OC0IDLRSTAT OC1IDLSTAT OC1IDLRSTAT OC2IDLSTAT OC2IDLRSTAT OC3IDLSTAT

OCPRLDEN : output compare control preload enable
bits : 0 - 0 (1 bit)
access : read-write

CUSRC : capture/compare update source
bits : 2 - 2 (1 bit)
access : read-write

OCDMASRC : output compare DMA source
bits : 3 - 3 (1 bit)
access : read-write

TRIGOSRC : trigger out source
bits : 4 - 6 (3 bit)
access : read-write

IS0SRC : input signal 0 source
bits : 7 - 7 (1 bit)
access : read-write

OC0IDLSTAT : output compare 0 idle mode status
bits : 8 - 8 (1 bit)
access : read-write

OC0IDLRSTAT : output compare 0 idle mode reversed status
bits : 9 - 9 (1 bit)
access : read-write

OC1IDLSTAT : output compare 1 idle mode status
bits : 10 - 10 (1 bit)
access : read-write

OC1IDLRSTAT : output compare 1 idle mode reversed status
bits : 11 - 11 (1 bit)
access : read-write

OC2IDLSTAT : output compare 2 idle mode status
bits : 12 - 12 (1 bit)
access : read-write

OC2IDLRSTAT : output compare 2 idle mode reversed status
bits : 13 - 13 (1 bit)
access : read-write

OC3IDLSTAT : output compare 3 idle mode status
bits : 14 - 14 (1 bit)
access : read-write


CCMP3

capture/compare counter value 3
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCMP3 CCMP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCMP3

CCMP3 : capture/compare counter value 3
bits : 0 - 15 (16 bit)
access : read-write


PROTCFG

protect configuration register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROTCFG PROTCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT FRZ OCIDLEN OCRUNEN BRKEN BRKPOL AOCEN OCEN

DT : dead time
bits : 0 - 7 (8 bit)
access : read-write

FRZ : freeze function
bits : 8 - 9 (2 bit)
access : read-write

OCIDLEN : output compare idle mode off-state enable
bits : 10 - 10 (1 bit)
access : read-write

OCRUNEN : output compare running mode off-state enable
bits : 11 - 11 (1 bit)
access : read-write

BRKEN : break enable
bits : 12 - 12 (1 bit)
access : read-write

BRKPOL : break input signal polarity level
bits : 13 - 13 (1 bit)
access : read-write

AOCEN : automatic output compare enable
bits : 14 - 14 (1 bit)
access : read-write

OCEN : output compare enable
bits : 15 - 15 (1 bit)
access : read-write


DMACFG

DMA configuration register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACFG DMACFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASEADDR BSTLEN

BASEADDR : DMA base address
bits : 0 - 4 (5 bit)
access : read-write

BSTLEN : DMA burst length
bits : 8 - 12 (5 bit)
access : read-write


DMARMP

DMA remap register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMARMP DMARMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMP

RMP : DMA burst remap address
bits : 0 - 15 (16 bit)
access : read-write


SLVMODCTL

slave control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLVMODCTL SLVMODCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLVMOD PREOUTCLR TRIGISRC SYNCEN EXTFLT EXTDIV EXTEN EXTPOL

SLVMOD : Slave mode
bits : 0 - 2 (3 bit)
access : read-write

PREOUTCLR : preout clear
bits : 3 - 3 (1 bit)
access : read-write

TRIGISRC : trigger input source
bits : 4 - 6 (3 bit)
access : read-write

SYNCEN : sync enable
bits : 7 - 7 (1 bit)
access : read-write

EXTFLT : external signal filter
bits : 8 - 11 (4 bit)
access : read-write

EXTDIV : external signal division
bits : 12 - 13 (2 bit)
access : read-write

EXTEN : external signal enable
bits : 14 - 14 (1 bit)
access : read-write

EXTPOL : external signal polarity level
bits : 15 - 15 (1 bit)
access : read-write


INTDMAEN

interrupt/DMA enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTDMAEN INTDMAEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UINTEN C0INTEN C1INTEN C2INTEN C3INTEN COMINTEN TRIGIINTEN BRKINTEN UDMAEN C0DMAEN C1DMAEN C2DMAEN C3DMAEN COMDMAEN TRIGIDMAEN

UINTEN : update interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

C0INTEN : capture/compare 0 interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

C1INTEN : capture/compare 1 interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

C2INTEN : capture/compare 2 interrupt enable
bits : 3 - 3 (1 bit)
access : read-write

C3INTEN : capture/compare 3 interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

COMINTEN : commutation interrupt enable
bits : 5 - 5 (1 bit)
access : read-write

TRIGIINTEN : trigger input interrupt enable
bits : 6 - 6 (1 bit)
access : read-write

BRKINTEN : break interrupt enable
bits : 7 - 7 (1 bit)
access : read-write

UDMAEN : update DMA enable
bits : 8 - 8 (1 bit)
access : read-write

C0DMAEN : capture/compare 0 DMA enable
bits : 9 - 9 (1 bit)
access : read-write

C1DMAEN : capture/compare 1 DMA enable
bits : 10 - 10 (1 bit)
access : read-write

C2DMAEN : capture/compare 2 DMA enable
bits : 11 - 11 (1 bit)
access : read-write

C3DMAEN : capture/compare 3 DMA enable
bits : 12 - 12 (1 bit)
access : read-write

COMDMAEN : commutation DMA enable
bits : 13 - 13 (1 bit)
access : read-write

TRIGIDMAEN : trigger input DMA enable
bits : 14 - 14 (1 bit)
access : read-write



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