\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Counter enable
bits : 0 - 0 (1 bit)
access : read-write
UDIS : Update disable
bits : 1 - 1 (1 bit)
access : read-write
USRC : Update source
bits : 2 - 2 (1 bit)
access : read-write
RLDPRLDEN : reload preload enable
bits : 7 - 7 (1 bit)
access : read-write
CLKDIV : clock division
bits : 8 - 9 (2 bit)
access : read-write
status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UF : update flag
bits : 0 - 0 (1 bit)
access : read-write
C0F : capture/compare 0 flag
bits : 1 - 1 (1 bit)
access : read-write
OVC0F : over capture 0 flag
bits : 9 - 9 (1 bit)
access : read-write
event set register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UPDATE : update event set
bits : 0 - 0 (1 bit)
access : write-only
C0 : capture/compare 0 event set
bits : 1 - 1 (1 bit)
access : write-only
capture/compare control register 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICS0SRC : input capture signal 0 source
bits : 0 - 1 (2 bit)
access : read-write
OCS0FMEN : output compare signal 0 Fast Mode enable
bits : 2 - 2 (1 bit)
access : read-write
OCS0PRLDEN : output compare signal 0 preload enable
bits : 3 - 3 (1 bit)
access : read-write
OCS0MOD : output compare signal 0 mode
bits : 4 - 6 (3 bit)
access : read-write
capture/compare control register 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCTL0_output
reset_Mask : 0x0
ICS0SRC : input capture signal 0 source
bits : 0 - 1 (2 bit)
access : read-write
ICS0DIV : input capture signal 0 division
bits : 2 - 3 (2 bit)
access : read-write
ICS0FLT : input capture signal 0 filter
bits : 4 - 7 (4 bit)
access : read-write
capture/compare control register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CS0EN : capture/compare signal 0 enable
bits : 0 - 0 (1 bit)
access : read-write
CS0POL : capture/compare signal 0 polarity level
bits : 1 - 1 (1 bit)
access : read-write
CS0RPOL : capture/compare signal 0 reverse polarity level
bits : 3 - 3 (1 bit)
access : read-write
timer' current data
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : timer data
bits : 0 - 15 (16 bit)
access : read-write
timer' divisions
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : timer divisions
bits : 0 - 15 (16 bit)
access : read-write
timer' reload
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RLD : timer reload
bits : 0 - 15 (16 bit)
access : read-write
capture/compare counter value 0
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCMP0 : capture/compare counter value 0
bits : 0 - 15 (16 bit)
access : read-write
option remap register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IS0RMP : input signal 0 option remap
bits : 0 - 1 (2 bit)
access : read-write
interrupt/DMA enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UINTEN : update interrupt enable
bits : 0 - 0 (1 bit)
access : read-write
C0INTEN : capture/compare 0 interrupt enable
bits : 1 - 1 (1 bit)
access : read-write
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