\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UEN : USART enable
bits : 0 - 0 (1 bit)
access : read-write
USMODEN : USART enable in stop mode
bits : 1 - 1 (1 bit)
access : read-write
RXEN : receive enable
bits : 2 - 2 (1 bit)
access : read-write
TXEN : transmit enable
bits : 3 - 3 (1 bit)
access : read-write
IDLEINTEN : idle interrupt enable
bits : 4 - 4 (1 bit)
access : read-write
RXNEINTEN : RXNE interrupt enable
bits : 5 - 5 (1 bit)
access : read-write
TXCINTEN : transfer complete interrupt enable
bits : 6 - 6 (1 bit)
access : read-write
TXEINTEN : transfer empty interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
PINTEN : parity interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
PSEL : parity selection
bits : 9 - 9 (1 bit)
access : read-write
PEN : parity control enable
bits : 10 - 10 (1 bit)
access : read-write
WUMMOD : mute mode wakeup method
bits : 11 - 11 (1 bit)
access : read-write
CLEN : char length
bits : 12 - 12 (1 bit)
access : read-write
MMODEN : mute mode enable
bits : 13 - 13 (1 bit)
access : read-write
CMINTEN : character match interrupt enable
bits : 14 - 14 (1 bit)
access : read-write
OVS8 : oversample by 8 enable
bits : 15 - 15 (1 bit)
access : read-write
DEDT : Driver Enable de-assertion time
bits : 16 - 20 (5 bit)
access : read-write
DEAT : Driver Enable assertion time
bits : 21 - 25 (5 bit)
access : read-write
RXTOINTEN : receive timeout interrupt enable
bits : 26 - 26 (1 bit)
access : read-write
IrDA prescale register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRDIV : prescale division
bits : 0 - 7 (8 bit)
access : read-write
receiver timeout value register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXTOVAL : receiver timeout value
bits : 0 - 23 (24 bit)
access : read-write
request register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ABRREQ : auto baud rate request
bits : 0 - 0 (1 bit)
access : write-only
SBRKREQ : send break request
bits : 1 - 1 (1 bit)
access : write-only
MMODREQ : mute mode request
bits : 2 - 2 (1 bit)
access : write-only
RXFREQ : receive data flush request
bits : 3 - 3 (1 bit)
access : write-only
Interrupt status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERRF : parity error flag
bits : 0 - 0 (1 bit)
access : read-only
FERRF : framing error flag
bits : 1 - 1 (1 bit)
access : read-only
NERRF : noise error flag
bits : 2 - 2 (1 bit)
access : read-only
OVRERRF : overrun error flag
bits : 3 - 3 (1 bit)
access : read-only
IDLEF : idle line detect
bits : 4 - 4 (1 bit)
access : read-only
RXNEF : read data register not empty flag
bits : 5 - 5 (1 bit)
access : read-only
TXCF : transmit complete flag
bits : 6 - 6 (1 bit)
access : read-only
TXEF : transmit data register empty flag
bits : 7 - 7 (1 bit)
access : read-only
LBDF : LIN break detection flag
bits : 8 - 8 (1 bit)
access : read-only
CTSINTF : CTS interrupt flag
bits : 9 - 9 (1 bit)
access : read-only
CTSF : CTS flag
bits : 10 - 10 (1 bit)
access : read-only
RXTOF : receive timeout flag
bits : 11 - 11 (1 bit)
access : read-only
ABRERRF : auto baud rate err flag
bits : 14 - 14 (1 bit)
access : read-only
ABRF : auto baud rate success flag
bits : 15 - 15 (1 bit)
access : read-only
BSYF : busy flag
bits : 16 - 16 (1 bit)
access : read-only
CMF : character match flag
bits : 17 - 17 (1 bit)
access : read-only
SBRKF : send break flag
bits : 18 - 18 (1 bit)
access : read-only
RXWUF : receiver wakeup from mute mode flag
bits : 19 - 19 (1 bit)
access : read-only
WUSTPMODF : wake up from stop mode flag
bits : 20 - 20 (1 bit)
access : read-only
TEACK : TE is taken into account
bits : 21 - 21 (1 bit)
access : read-only
REACK : RE is taken into account
bits : 22 - 22 (1 bit)
access : read-only
Interrupts clear register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PERRCLR : parity error clear flag
bits : 0 - 0 (1 bit)
access : write-only
FERRCLR : framing error clear flag
bits : 1 - 1 (1 bit)
access : write-only
NERRCLR : noise detected clear flag
bits : 2 - 2 (1 bit)
access : write-only
OVRERRCLR : overrun error clear flag
bits : 3 - 3 (1 bit)
access : write-only
IDLEFCLR : idle line detected clear flag
bits : 4 - 4 (1 bit)
access : write-only
TXCFCLR : transmission complete clear flag
bits : 6 - 6 (1 bit)
access : write-only
LBDFCLR : LIN break detection clear flag
bits : 8 - 8 (1 bit)
access : write-only
CTSINTFCLR : CTS clear flag
bits : 9 - 9 (1 bit)
access : write-only
RXTOFCLR : receive timeout clear flag
bits : 11 - 11 (1 bit)
access : write-only
CMFCLR : character match clear flag
bits : 17 - 17 (1 bit)
access : write-only
WUSTPMODFCLR : wakeup from stop mode clear flag
bits : 20 - 20 (1 bit)
access : write-only
receive data register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX buffer data
bits : 0 - 8 (9 bit)
access : read-only
transmit data register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX buffer data
bits : 0 - 8 (9 bit)
access : read-write
control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRM : address detection mode
bits : 4 - 4 (1 bit)
access : read-write
LBDLEN : LIN break detection length
bits : 5 - 5 (1 bit)
access : read-write
LBDINTEN : LIN break detection interrupt enable
bits : 6 - 6 (1 bit)
access : read-write
LBCLK : last bit clock pulse
bits : 8 - 8 (1 bit)
access : read-write
CPHA : clock phase
bits : 9 - 9 (1 bit)
access : read-write
CPOL : clock polarity
bits : 10 - 10 (1 bit)
access : read-write
CLKEN : clock enable
bits : 11 - 11 (1 bit)
access : read-write
STOPBIT : stop bits
bits : 12 - 13 (2 bit)
access : read-write
LINEN : LIN mode enable
bits : 14 - 14 (1 bit)
access : read-write
SWAPTXRX : Swap TX/RX pins
bits : 15 - 15 (1 bit)
access : read-write
RXINV : RX pin signals are inverted
bits : 16 - 16 (1 bit)
access : read-write
TXINV : TX pin signals are inverted
bits : 17 - 17 (1 bit)
access : read-write
DATINV : data and parity bit are inverted
bits : 18 - 18 (1 bit)
access : read-write
MSBFST : MSB first
bits : 19 - 19 (1 bit)
access : read-write
ABREN : auto baud rate enable
bits : 20 - 20 (1 bit)
access : read-write
ABRMOD : auto baud rate mode
bits : 21 - 22 (2 bit)
access : read-write
RXTOEN : receiver timeout enable
bits : 23 - 23 (1 bit)
access : read-write
ADDR : address of the USART node
bits : 24 - 31 (8 bit)
access : read-write
control register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERRINTEN : error interrupt enable
bits : 0 - 0 (1 bit)
access : read-write
IRMODEN : IrDA mode enable
bits : 1 - 1 (1 bit)
access : read-write
IRMODLP : IrDA low power mode enable
bits : 2 - 2 (1 bit)
access : read-write
HFDUPSEL : half duplex selection
bits : 3 - 3 (1 bit)
access : read-write
DMARXEN : DMA enable receiver
bits : 6 - 6 (1 bit)
access : read-write
DMATXEN : DMA enable transmitter
bits : 7 - 7 (1 bit)
access : read-write
RTSEN : RTS enable
bits : 8 - 8 (1 bit)
access : read-write
CTSEN : CTS enable
bits : 9 - 9 (1 bit)
access : read-write
CTSINTEN : CTS interrupt enable
bits : 10 - 10 (1 bit)
access : read-write
ONEBITEN : one bit enable
bits : 11 - 11 (1 bit)
access : read-write
OVRDIS : overrun disable
bits : 12 - 12 (1 bit)
access : read-write
DDRE : DMA disable on reception error
bits : 13 - 13 (1 bit)
access : read-write
DEEN : driver enable mode
bits : 14 - 14 (1 bit)
access : read-write
DEPSEL : DE signal polarity
bits : 15 - 15 (1 bit)
access : read-write
WUSTPMOD : wakeup from stop mode
bits : 20 - 21 (2 bit)
access : read-write
WUSTPMODINTEN : wakeup from stop mode interrupt enable
bits : 22 - 22 (1 bit)
access : read-write
baud rate register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRDIV : baud rate division
bits : 0 - 15 (16 bit)
access : read-write
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