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AES

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x84 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL

XFE_SIZE

RD_START_ADDR

WR_START_ADDR

KEY_ADDR

DATA_OUT0

DATA_OUT1

DATA_OUT2

DATA_OUT3

KEY0

KEY1

KEY2

KEY3

CFG

KEY4

KEY5

KEY6

KEY7

INIT_SSI

INIT_SSO

MASK_SSI

MASK_SSO

INIT_V0

INIT_V1

INIT_V2

INIT_V3

DATA_IN0

DATA_IN1

DATA_IN2

DATA_IN3

STAT

KEYPORT_MASK

INT


CTRL

AES Controller Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCU_MODE_EN DMA_MODE_EN FKEY_EN

MCU_MODE_EN : MCU mode start enable: MCU mode start a block data encryption or decryption. This signal should be clear to zero before a new block input data is ready to start.
bits : 1 - 1 (1 bit)
access : read-write

DMA_MODE_EN : DMA mode start enable: DMA mode start N block data encryption or decryption.
bits : 2 - 2 (1 bit)
access : read-write

FKEY_EN : Enable AES fetch key by itself through AHBAHB master interface or key port. This register can be cleared by itself when key_valid is set to 1.
bits : 3 - 3 (1 bit)
access : write-only


XFE_SIZE

AES Transfer Size Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XFE_SIZE XFE_SIZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE

SIZE : Total transfer size, up to 32KB 0x000f: 1 block 0x001f: 2 block 0x002f: 3 block -- 0x7fff: 2048 block
bits : 0 - 14 (15 bit)
access : read-write


RD_START_ADDR

AES Read Start Address Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RD_START_ADDR RD_START_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : DMA mode, read start address of transfer
bits : 0 - 31 (32 bit)
access : read-write


WR_START_ADDR

AES Write Start Address Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WR_START_ADDR WR_START_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : DMA mode, write start address of transfer
bits : 0 - 31 (32 bit)
access : read-write


KEY_ADDR

AES Key Address Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEY_ADDR KEY_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : AES Key Address Register
bits : 0 - 31 (32 bit)
access : read-write


DATA_OUT0

AES Data Output 0 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DATA_OUT0 DATA_OUT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_OUT0

DATA_OUT0 : AES result data[127:96]
bits : 0 - 31 (32 bit)
access : read-only


DATA_OUT1

AES Data Output 1 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DATA_OUT1 DATA_OUT1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_OUT1

DATA_OUT1 : AES result data[95:64]
bits : 0 - 31 (32 bit)
access : read-only


DATA_OUT2

AES Data Output 2 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DATA_OUT2 DATA_OUT2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_OUT2

DATA_OUT2 : AES result data[63:32]
bits : 0 - 31 (32 bit)
access : read-only


DATA_OUT3

AES Data Output 3 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DATA_OUT3 DATA_OUT3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_OUT3

DATA_OUT3 : AES result data[31:0]
bits : 0 - 31 (32 bit)
access : read-only


KEY0

AES Key 0 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY0 KEY0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY0

KEY0 : AES key[255:224]
bits : 0 - 31 (32 bit)
access : write-only


KEY1

AES Key 1 Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY1 KEY1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY1

KEY1 : AES key[223:192]
bits : 0 - 31 (32 bit)
access : write-only


KEY2

AES Key 2 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY2 KEY2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY2

KEY2 : AES key[191:160]
bits : 0 - 31 (32 bit)
access : write-only


KEY3

AES Key 3 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY3 KEY3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY3

KEY3 : AES key[159:128]
bits : 0 - 31 (32 bit)
access : write-only


CFG

AES Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY_MODE FULL_MASK_EN DEC_ENC_SEL LOAD_SEED FIRST_BLK ENDIAN OPT_MODE KEY_TYPE

KEY_MODE : Key mode selection for encryption / decryption 0x0: 128 bits (default) 0x1: 192 bits 0x2: 256 bits 0x3: Reserved
bits : 0 - 1 (2 bit)
access : read-write

FULL_MASK_EN : Full mask enable signal 0x0: Disable (default) 0x1: Enable (DPA Resistance)
bits : 3 - 3 (1 bit)
access : read-write

DEC_ENC_SEL : Selection for encryption/decryption 0x0: Decryption(default) 0x1: Encryption
bits : 4 - 4 (1 bit)
access : read-write

LOAD_SEED : Load seed for LFSR, seed for LFSR will be reloaded when this register was written with 1. This register can be cleared by itself.
bits : 5 - 5 (1 bit)
access : write-only

FIRST_BLK : This register should be set to 1 before starting the first block in normal CBC and DMA CBC mode, and this register will be cleared by itself.
bits : 6 - 6 (1 bit)
access : write-only

ENDIAN : Selection for data endian ctrl 0x0: Reverse to big_endian(default) 0x1: No reverse
bits : 7 - 7 (1 bit)
access : read-write

OPT_MODE : Selection for operation mode 0x0: Electronic codebook (ECB) mode 0x1: Cipher block chaining (CBC) mode 0x2 ~ 0x7: Reserved for future application
bits : 8 - 10 (3 bit)
access : read-write

KEY_TYPE : key type selection for encryption / decryption 0x0: Configured by MCU(default) 0x1: Fetched through AHB interface 0x2: Fetched through key port 0x3: Reserved
bits : 11 - 12 (2 bit)
access : read-write


KEY4

AES Key 4 Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY4 KEY4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY4

KEY4 : AES key[127:96]
bits : 0 - 31 (32 bit)
access : write-only


KEY5

AES Key 5 Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY5 KEY5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY5

KEY5 : AES key[95:64]
bits : 0 - 31 (32 bit)
access : write-only


KEY6

AES Key 6 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY6 KEY6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY6

KEY6 : AES key[63:32]
bits : 0 - 31 (32 bit)
access : write-only


KEY7

AES Key 7 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY7 KEY7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY7

KEY7 : AES key[31:0]
bits : 0 - 31 (32 bit)
access : write-only


INIT_SSI

AES Sbox Initial Seed Input Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INIT_SSI INIT_SSI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEED

SEED : Sbox initial seed input
bits : 0 - 31 (32 bit)
access : read-write


INIT_SSO

AES Sbox Initial Seed Output Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INIT_SSO INIT_SSO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEED

SEED : Sbox initial seed onput
bits : 0 - 31 (32 bit)
access : read-write


MASK_SSI

AES Sbox Seed Input Mask Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASK_SSI MASK_SSI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Sbox initial seed input mask
bits : 0 - 31 (32 bit)
access : read-write


MASK_SSO

AES Sbox Seed Input Mask Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASK_SSO MASK_SSO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Sbox initial seed output mask
bits : 0 - 31 (32 bit)
access : read-write


INIT_V0

AES Initialization Vector 0 Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INIT_V0 INIT_V0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTOR

VECTOR : Initialization vector[127:96] for CBC mode
bits : 0 - 31 (32 bit)
access : write-only


INIT_V1

AES Initialization Vector 1 Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INIT_V1 INIT_V1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTOR

VECTOR : Initialization vector[95:64] for CBC mode
bits : 0 - 31 (32 bit)
access : write-only


INIT_V2

AES Initialization Vector 2 Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INIT_V2 INIT_V2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTOR

VECTOR : Initialization vector[63:32] for CBC mode
bits : 0 - 31 (32 bit)
access : write-only


INIT_V3

AES Initialization Vector 3 Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INIT_V3 INIT_V3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTOR

VECTOR : Initialization vector[31:0] for CBC mode
bits : 0 - 31 (32 bit)
access : write-only


DATA_IN0

AES Data Input 0 Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DATA_IN0 DATA_IN0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_IN0

DATA_IN0 : Input data[127:96] for encryption or decryption. This register is valid in MUC mode.
bits : 0 - 31 (32 bit)
access : write-only


DATA_IN1

AES Data Input 1 Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DATA_IN1 DATA_IN1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_IN1

DATA_IN1 : Input data[95:64] for encryption or decryption. This register is valid in MUC mode.
bits : 0 - 31 (32 bit)
access : write-only


DATA_IN2

AES Data Input 2 Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DATA_IN2 DATA_IN2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_IN2

DATA_IN2 : Input data[63:32] for encryption or decryption. This register is valid in MUC mode.
bits : 0 - 31 (32 bit)
access : write-only


DATA_IN3

AES Data Input 3 Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DATA_IN3 DATA_IN3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_IN3

DATA_IN3 : Input data[31:0] for encryption or decryption. This register is valid in MUC mode.
bits : 0 - 31 (32 bit)
access : write-only


STAT

AES Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READY DMA_XFE_CPLT DMA_XFE_ERR KEY_STAT

READY : AES result data out ready or not. This signal may be cleared when MCU_MODE_EN(CTRL[1]) is disabled. 0x0: Not ready 0x1 : Ready
bits : 0 - 0 (1 bit)
access : read-only

DMA_XFE_CPLT : DMA transfer complete 0x0: Not complete 0x1: Complete
bits : 1 - 1 (1 bit)
access : read-only

DMA_XFE_ERR : DMA transfer error, Write 1 to clear 0x0: Not ready 0x1: Ready
bits : 2 - 2 (1 bit)
access : read-only

KEY_STAT : Key status, key is ready to read or not 0x0: Not ready 0x1: Ready
bits : 3 - 3 (1 bit)
access : read-only


KEYPORT_MASK

AES Keyport Mask Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYPORT_MASK KEYPORT_MASK write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Mask for key from keyport
bits : 0 - 31 (32 bit)
access : write-only


INT

AES Interrupt Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPLT_INT_FLAG CPLT_INT_EN

CPLT_INT_FLAG : AES result data complete interrupt flag. Write 1 to clear. Read 0x0: Not interrupt 0x1: Interrupt Write 0x0: Not effect 0x1: Clear
bits : 0 - 0 (1 bit)
access : read-write

CPLT_INT_EN : AES result data complete interrupt 0x0: Disable 0x1: Enable
bits : 1 - 1 (1 bit)
access : read-write



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