Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1E8 byte (0x0)
mem_usage : registers
protection :
Source Address for Channel 0 LOW 32 bit
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_ADDR : Current Source Address of DMA transfer. Updated after each source transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true
bits : 0 - 31 (32 bit)
access : read-write
Source Address for Channel 3 LOW 32 bit
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_ADDR : Current Source Address of DMA transfer. Updated after each source transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true
bits : 0 - 31 (32 bit)
access : read-write
Source Address for Channel 3 High 32 bit
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register for Channel 3 Low 32 bit
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEST_ADDR : Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true
bits : 0 - 31 (32 bit)
access : read-write
Destination Address Register for Channel 3 High 32 bit
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Control Register for Channel 3 Low 32 bit
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_EN : Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel raw* interrupt registers still assert if CTRLx.INT_EN=0. 0x0: Interrupt is disabled 0x1: Interrupt is enabled Volatile: true
bits : 0 - 0 (1 bit)
access : read-write
DEST_XFE_WIDTH : Destination Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. 0x0: Destination transfer width is 8 bits 0x1: Destination transfer width is 16 bits 0x2: Destination transfer width is 32 bits Volatile: true
bits : 1 - 3 (3 bit)
access : read-write
SRC_XFE_WIDTH : Source Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. 0x0: Source transfer width is 8 bits 0x1: Source transfer width is 16 bits 0x2: Source transfer width is 32 bits Volatile: true
bits : 4 - 6 (3 bit)
access : read-write
DEST_ADDR_INC : Destination Address Increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No Change . 0x0: Increments the destination address 0x1: Decrements the destination address 0x2: No change in the destination address 0x3: No change in the destination address Volatile: true
bits : 7 - 8 (2 bit)
access : read-write
SRC_ADDR_INC : Source Address Increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change . 0x0: Increments the source address 0x1: Decrements the source address 0x2: No change in the source address 0x3: No change in the source address Volatile: true
bits : 9 - 10 (2 bit)
access : read-write
DEST_MSIZE : Destination Burst Transaction Length. Number of data items, each of width CTRL_CHx.DEST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true
bits : 11 - 13 (3 bit)
access : read-write
SRC_MSIZE : Source Burst Transaction Length. Number of data items, each of width CTRL_CHx.SRC_TR_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true
bits : 14 - 16 (3 bit)
access : read-write
XFE_TYPE_FC : Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. • 0x0: Transfer type is Memory to Memory and Flow Controller is DMA • 0x1: Transfer type is Memory to Peripheral and Flow Controller is DMA • 0x2: Transfer type is Peripheral to Memory and Flow Controller is DMA • 0x3: Transfer type is Peripheral to Peripheral and Flow Controller is DMA Volatile: true
bits : 20 - 22 (3 bit)
access : read-write
Control Register for Channel 3 High 32 bit
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLOCK_XFE_SIZE : Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_TR_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what is the flow controller. When the source or destination peripheral is assigned as the flow controller, then the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true
bits : 0 - 4 (5 bit)
access : read-write
DONE : Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx [63:32], is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer is complete. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize=2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. For more information, refer to Multi-Block Transfers . Volatile: true
bits : 12 - 12 (1 bit)
access : read-write
Configuration Register for Channel 3 Low 32 bit
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_PRIOR : Channel Priority. A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the range 0 to 3. A programmed value outside this range will cause erroneous behavior. 0x0: Channel priority is 0 0x1: Channel priority is 1 0x2: Channel priority is 2 0x3: Channel priority is 3
bits : 5 - 7 (3 bit)
access : read-write
CH_SUSP : Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFG_CHx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0x0: DMA transfer from the source is not suspended 0x1: Suspend DMA transfer from the source
bits : 8 - 8 (1 bit)
access : read-write
FIFO_EMPTY : Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty
bits : 9 - 9 (1 bit)
access : read-only
HSG_SEL_DEST : Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, then this bit is ignored. 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored.
bits : 10 - 10 (1 bit)
access : read-write
HSG_SEL_SRC : Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFG_CHx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty
bits : 11 - 11 (1 bit)
access : read-write
DEST_HSG_POL : Destination Handshaking Interface Polarity. 0x0: Destination Handshaking Interface Polarity is Active high 0x1: Destination Handshaking Interface Polarity is Active low
bits : 18 - 18 (1 bit)
access : read-write
SRC_HSG_POL : Source Handshaking Interface Polarity. 0x0: Source Handshaking Interface Polarity is Active high 0x1: Source Handshaking Interface Polarity is Active low
bits : 19 - 19 (1 bit)
access : read-write
RELOAD_SRC : Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Source Reload Disabled 0x1: Source Reload Enabled
bits : 30 - 30 (1 bit)
access : read-write
RELOAD_DEST : Automatic Destination Reload. The DEST_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Destination Reload Disabled. 0x1: Destination Reload Enabled
bits : 31 - 31 (1 bit)
access : read-write
Configuration Register for Channel 3 High 32 bit
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLOW_CTRL_MODE : Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0x0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled 0x1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled.
bits : 0 - 0 (1 bit)
access : read-write
FIFO_MODE : FIFO Mode Select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0x0: Space/data available for single AHB transfer of the specified transfer width 0x1: Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer.
bits : 1 - 1 (1 bit)
access : read-write
PROT_CTRL : Protection Control bits used to drive the AHB HPROT[3:1] bus. The AMBA Specification recommends that the default of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows: • 0x1 to HPROT[0] • CFGx.PROTCTL[1] to HPROT[1] • CFGx.PROTCTL[2] to HPROT[2] • CFGx.PROTCTL[3] to HPROT[3]
bits : 2 - 4 (3 bit)
access : read-write
SRC_PER : Source Hardware Interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0 otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
bits : 7 - 10 (4 bit)
access : read-write
DEST_PER : Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFGx.HSG_SEL_DST field is 0 otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
bits : 11 - 14 (4 bit)
access : read-write
Source Address for Channel 4 LOW 32 bit
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_ADDR : Current Source Address of DMA transfer. Updated after each source transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true
bits : 0 - 31 (32 bit)
access : read-write
Source Address for Channel 4 High 32 bit
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register for Channel 4 Low 32 bit
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEST_ADDR : Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true
bits : 0 - 31 (32 bit)
access : read-write
Destination Address Register for Channel 4 High 32 bit
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Control Register for Channel 4 Low 32 bit
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_EN : Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel raw* interrupt registers still assert if CTRLx.INT_EN=0. 0x0: Interrupt is disabled 0x1: Interrupt is enabled Volatile: true
bits : 0 - 0 (1 bit)
access : read-write
DEST_XFE_WIDTH : Destination Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. 0x0: Destination transfer width is 8 bits 0x1: Destination transfer width is 16 bits 0x2: Destination transfer width is 32 bits Volatile: true
bits : 1 - 3 (3 bit)
access : read-write
SRC_XFE_WIDTH : Source Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. 0x0: Source transfer width is 8 bits 0x1: Source transfer width is 16 bits 0x2: Source transfer width is 32 bits Volatile: true
bits : 4 - 6 (3 bit)
access : read-write
DEST_ADDR_INC : Destination Address Increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No Change . 0x0: Increments the destination address 0x1: Decrements the destination address 0x2: No change in the destination address 0x3: No change in the destination address Volatile: true
bits : 7 - 8 (2 bit)
access : read-write
SRC_ADDR_INC : Source Address Increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change . 0x0: Increments the source address 0x1: Decrements the source address 0x2: No change in the source address 0x3: No change in the source address Volatile: true
bits : 9 - 10 (2 bit)
access : read-write
DEST_MSIZE : Destination Burst Transaction Length. Number of data items, each of width CTRL_CHx.DEST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true
bits : 11 - 13 (3 bit)
access : read-write
SRC_MSIZE : Source Burst Transaction Length. Number of data items, each of width CTRL_CHx.SRC_TR_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true
bits : 14 - 16 (3 bit)
access : read-write
XFE_TYPE_FC : Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. • 0x0: Transfer type is Memory to Memory and Flow Controller is DMA • 0x1: Transfer type is Memory to Peripheral and Flow Controller is DMA • 0x2: Transfer type is Peripheral to Memory and Flow Controller is DMA • 0x3: Transfer type is Peripheral to Peripheral and Flow Controller is DMA Volatile: true
bits : 20 - 22 (3 bit)
access : read-write
Control Register for Channel 4 High 32 bit
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLOCK_XFE_SIZE : Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_TR_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what is the flow controller. When the source or destination peripheral is assigned as the flow controller, then the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true
bits : 0 - 4 (5 bit)
access : read-write
DONE : Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx [63:32], is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer is complete. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize=2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. For more information, refer to Multi-Block Transfers . Volatile: true
bits : 12 - 12 (1 bit)
access : read-write
Control Register for Channel 0 Low 32 bit
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_EN : Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel raw* interrupt registers still assert if CTRLx.INT_EN=0. 0x0: Interrupt is disabled 0x1: Interrupt is enabled Volatile: true
bits : 0 - 0 (1 bit)
access : read-write
DEST_XFE_WIDTH : Destination Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. 0x0: Destination transfer width is 8 bits 0x1: Destination transfer width is 16 bits 0x2: Destination transfer width is 32 bits Volatile: true
bits : 1 - 3 (3 bit)
access : read-write
SRC_XFE_WIDTH : Source Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. 0x0: Source transfer width is 8 bits 0x1: Source transfer width is 16 bits 0x2: Source transfer width is 32 bits Volatile: true
bits : 4 - 6 (3 bit)
access : read-write
DEST_ADDR_INC : Destination Address Increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No Change . 0x0: Increments the destination address 0x1: Decrements the destination address 0x2: No change in the destination address 0x3: No change in the destination address Volatile: true
bits : 7 - 8 (2 bit)
access : read-write
SRC_ADDR_INC : Source Address Increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change . 0x0: Increments the source address 0x1: Decrements the source address 0x2: No change in the source address 0x3: No change in the source address Volatile: true
bits : 9 - 10 (2 bit)
access : read-write
DEST_MSIZE : Destination Burst Transaction Length. Number of data items, each of width CTRL_CHx.DEST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true
bits : 11 - 13 (3 bit)
access : read-write
SRC_MSIZE : Source Burst Transaction Length. Number of data items, each of width CTRL_CHx.SRC_TR_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true
bits : 14 - 16 (3 bit)
access : read-write
XFE_TYPE_FC : Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. • 0x0: Transfer type is Memory to Memory and Flow Controller is DMA • 0x1: Transfer type is Memory to Peripheral and Flow Controller is DMA • 0x2: Transfer type is Peripheral to Memory and Flow Controller is DMA • 0x3: Transfer type is Peripheral to Peripheral and Flow Controller is DMA Volatile: true
bits : 20 - 22 (3 bit)
access : read-write
Configuration Register for Channel 4 Low 32 bit
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_PRIOR : Channel Priority. A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the range 0 to 3. A programmed value outside this range will cause erroneous behavior. 0x0: Channel priority is 0 0x1: Channel priority is 1 0x2: Channel priority is 2 0x3: Channel priority is 3
bits : 5 - 7 (3 bit)
access : read-write
CH_SUSP : Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFG_CHx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0x0: DMA transfer from the source is not suspended 0x1: Suspend DMA transfer from the source
bits : 8 - 8 (1 bit)
access : read-write
FIFO_EMPTY : Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty
bits : 9 - 9 (1 bit)
access : read-only
HSG_SEL_DEST : Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, then this bit is ignored. 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored.
bits : 10 - 10 (1 bit)
access : read-write
HSG_SEL_SRC : Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFG_CHx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty
bits : 11 - 11 (1 bit)
access : read-write
DEST_HSG_POL : Destination Handshaking Interface Polarity. 0x0: Destination Handshaking Interface Polarity is Active high 0x1: Destination Handshaking Interface Polarity is Active low
bits : 18 - 18 (1 bit)
access : read-write
SRC_HSG_POL : Source Handshaking Interface Polarity. 0x0: Source Handshaking Interface Polarity is Active high 0x1: Source Handshaking Interface Polarity is Active low
bits : 19 - 19 (1 bit)
access : read-write
RELOAD_SRC : Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Source Reload Disabled 0x1: Source Reload Enabled
bits : 30 - 30 (1 bit)
access : read-write
RELOAD_DEST : Automatic Destination Reload. The DEST_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Destination Reload Disabled. 0x1: Destination Reload Enabled
bits : 31 - 31 (1 bit)
access : read-write
Configuration Register for Channel 4 High 32 bit
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLOW_CTRL_MODE : Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0x0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled 0x1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled.
bits : 0 - 0 (1 bit)
access : read-write
FIFO_MODE : FIFO Mode Select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0x0: Space/data available for single AHB transfer of the specified transfer width 0x1: Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer.
bits : 1 - 1 (1 bit)
access : read-write
PROT_CTRL : Protection Control bits used to drive the AHB HPROT[3:1] bus. The AMBA Specification recommends that the default of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows • 0x1 to HPROT[0] • CFGx.PROTCTL[1] to HPROT[1] • CFGx.PROTCTL[2] to HPROT[2] • CFGx.PROTCTL[3] to HPROT[3]
bits : 2 - 4 (3 bit)
access : read-write
SRC_PER : Source Hardware Interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0 otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
bits : 7 - 10 (4 bit)
access : read-write
DEST_PER : Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFGx.HSG_SEL_DST field is 0 otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
bits : 11 - 14 (4 bit)
access : read-write
Source Address for Channel 5 LOW 32 bit
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_ADDR : Current Source Address of DMA transfer. Updated after each source transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true
bits : 0 - 31 (32 bit)
access : read-write
Source Address for Channel 5 High 32 bit
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Control Register for Channel 0 High 32 bit
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLOCK_XFE_SIZE : Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_TR_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what is the flow controller. When the source or destination peripheral is assigned as the flow controller, then the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true
bits : 0 - 4 (5 bit)
access : read-write
DONE : Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx [63:32], is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer is complete. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize=2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. For more information, refer to Multi-Block Transfers . Volatile: true
bits : 12 - 12 (1 bit)
access : read-write
Destination Address Register for Channel 5 Low 32 bit
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEST_ADDR : Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true
bits : 0 - 31 (32 bit)
access : read-write
Destination Address Register for Channel 5 High 32 bit
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Control Register for Channel 5 Low 32 bit
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_EN : Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel raw* interrupt registers still assert if CTRLx.INT_EN=0. 0x0: Interrupt is disabled 0x1: Interrupt is enabled Volatile: true
bits : 0 - 0 (1 bit)
access : read-write
DEST_XFE_WIDTH : Destination Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. 0x0: Destination transfer width is 8 bits 0x1: Destination transfer width is 16 bits 0x2: Destination transfer width is 32 bits Volatile: true
bits : 1 - 3 (3 bit)
access : read-write
SRC_XFE_WIDTH : Source Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. 0x0: Source transfer width is 8 bits 0x1: Source transfer width is 16 bits 0x2: Source transfer width is 32 bits Volatile: true
bits : 4 - 6 (3 bit)
access : read-write
DEST_ADDR_INC : Destination Address Increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No Change . 0x0: Increments the destination address 0x1: Decrements the destination address 0x2: No change in the destination address 0x3: No change in the destination address Volatile: true
bits : 7 - 8 (2 bit)
access : read-write
SRC_ADDR_INC : Source Address Increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change . 0x0: Increments the source address 0x1: Decrements the source address 0x2: No change in the source address 0x3: No change in the source address Volatile: true
bits : 9 - 10 (2 bit)
access : read-write
DEST_MSIZE : Destination Burst Transaction Length. Number of data items, each of width CTRL_CHx.DEST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true
bits : 11 - 13 (3 bit)
access : read-write
SRC_MSIZE : Source Burst Transaction Length. Number of data items, each of width CTRL_CHx.SRC_TR_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true
bits : 14 - 16 (3 bit)
access : read-write
XFE_TYPE_FC : Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. • 0x0: Transfer type is Memory to Memory and Flow Controller is DMA • 0x1: Transfer type is Memory to Peripheral and Flow Controller is DMA • 0x2: Transfer type is Peripheral to Memory and Flow Controller is DMA • 0x3: Transfer type is Peripheral to Peripheral and Flow Controller is DMA Volatile: true
bits : 20 - 22 (3 bit)
access : read-write
Control Register for Channel 5 High 32 bit
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLOCK_XFE_SIZE : Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_TR_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what is the flow controller. When the source or destination peripheral is assigned as the flow controller, then the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true
bits : 0 - 4 (5 bit)
access : read-write
DONE : Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx [63:32], is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer is complete. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize=2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. For more information, refer to Multi-Block Transfers . Volatile: true
bits : 12 - 12 (1 bit)
access : read-write
Configuration Register for Channel 5 Low 32 bit
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_PRIOR : Channel Priority. A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the range 0 to 3. A programmed value outside this range will cause erroneous behavior. 0x0: Channel priority is 0 0x1: Channel priority is 1 0x2: Channel priority is 2 0x3: Channel priority is 3
bits : 5 - 7 (3 bit)
access : read-write
CH_SUSP : Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFG_CHx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0x0: DMA transfer from the source is not suspended 0x1: Suspend DMA transfer from the source
bits : 8 - 8 (1 bit)
access : read-write
FIFO_EMPTY : Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty
bits : 9 - 9 (1 bit)
access : read-only
HSG_SEL_DEST : Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, then this bit is ignored. 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored.
bits : 10 - 10 (1 bit)
access : read-write
HSG_SEL_SRC : Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFG_CHx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty
bits : 11 - 11 (1 bit)
access : read-write
DEST_HSG_POL : Destination Handshaking Interface Polarity. 0x0: Destination Handshaking Interface Polarity is Active high 0x1: Destination Handshaking Interface Polarity is Active low
bits : 18 - 18 (1 bit)
access : read-write
SRC_HSG_POL : Source Handshaking Interface Polarity. 0x0: Source Handshaking Interface Polarity is Active high 0x1: Source Handshaking Interface Polarity is Active low
bits : 19 - 19 (1 bit)
access : read-write
RELOAD_SRC : Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Source Reload Disabled 0x1: Source Reload Enabled
bits : 30 - 30 (1 bit)
access : read-write
RELOAD_DEST : Automatic Destination Reload. The DEST_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Destination Reload Disabled. 0x1: Destination Reload Enabled
bits : 31 - 31 (1 bit)
access : read-write
Configuration Register for Channel 5 High 32 bit
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLOW_CTRL_MODE : Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0x0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled 0x1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled.
bits : 0 - 0 (1 bit)
access : read-write
FIFO_MODE : FIFO Mode Select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0x0: Space/data available for single AHB transfer of the specified transfer width 0x1: Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer.
bits : 1 - 1 (1 bit)
access : read-write
PROT_CTRL : Protection Control bits used to drive the AHB HPROT[3:1] bus. The AMBA Specification recommends that the default of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows • 0x1 to HPROT[0] • CFGx.PROTCTL[1] to HPROT[1] • CFGx.PROTCTL[2] to HPROT[2] • CFGx.PROTCTL[3] to HPROT[3]
bits : 2 - 4 (3 bit)
access : read-write
SRC_PER : Source Hardware Interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0 otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
bits : 7 - 10 (4 bit)
access : read-write
DEST_PER : Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFGx.HSG_SEL_DST field is 0 otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
bits : 11 - 14 (4 bit)
access : read-write
Source Address for Channel 6 Low 32 bit
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_ADDR : Current Source Address of DMA transfer. Updated after each source transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true
bits : 0 - 31 (32 bit)
access : read-write
Source Address for Channel 6 High 32 bit
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register for Channel 6 Low 32bit
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEST_ADDR : Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true
bits : 0 - 31 (32 bit)
access : read-write
Destination Address Register for Channel 6 High 32bit
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Control Register for Channel 6 Low 32 bit
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_EN : Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel raw* interrupt registers still assert if CTRLx.INT_EN=0. 0x0: Interrupt is disabled 0x1: Interrupt is enabled Volatile: true
bits : 0 - 0 (1 bit)
access : read-write
DEST_XFE_WIDTH : Destination Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. 0x0: Destination transfer width is 8 bits 0x1: Destination transfer width is 16 bits 0x2: Destination transfer width is 32 bits Volatile: true
bits : 1 - 3 (3 bit)
access : read-write
SRC_XFE_WIDTH : Source Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. 0x0: Source transfer width is 8 bits 0x1: Source transfer width is 16 bits 0x2: Source transfer width is 32 bits Volatile: true
bits : 4 - 6 (3 bit)
access : read-write
DEST_ADDR_INC : Destination Address Increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No Change . 0x0: Increments the destination address 0x1: Decrements the destination address 0x2: No change in the destination address 0x3: No change in the destination address Volatile: true
bits : 7 - 8 (2 bit)
access : read-write
SRC_ADDR_INC : Source Address Increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change . 0x0: Increments the source address 0x1: Decrements the source address 0x2: No change in the source address 0x3: No change in the source address Volatile: true
bits : 9 - 10 (2 bit)
access : read-write
DEST_MSIZE : Destination Burst Transaction Length. Number of data items, each of width CTRL_CHx.DEST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true
bits : 11 - 13 (3 bit)
access : read-write
SRC_MSIZE : Source Burst Transaction Length. Number of data items, each of width CTRL_CHx.SRC_TR_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true
bits : 14 - 16 (3 bit)
access : read-write
XFE_TYPE_FC : Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. • 0x0: Transfer type is Memory to Memory and Flow Controller is DMA • 0x1: Transfer type is Memory to Peripheral and Flow Controller is DMA • 0x2: Transfer type is Peripheral to Memory and Flow Controller is DMA • 0x3: Transfer type is Peripheral to Peripheral and Flow Controller is DMA Volatile: true
bits : 20 - 22 (3 bit)
access : read-write
Control Register for Channel 6 High 32 bit
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLOCK_XFE_SIZE : Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_TR_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what is the flow controller. When the source or destination peripheral is assigned as the flow controller, then the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true
bits : 0 - 4 (5 bit)
access : read-write
DONE : Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx [63:32], is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer is complete. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize=2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. For more information, refer to Multi-Block Transfers . Volatile: true
bits : 12 - 12 (1 bit)
access : read-write
Configuration Register for Channel 6 low 32 bit
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_PRIOR : Channel Priority. A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the range 0 to 3. A programmed value outside this range will cause erroneous behavior. 0x0: Channel priority is 0 0x1: Channel priority is 1 0x2: Channel priority is 2 0x3: Channel priority is 3
bits : 5 - 7 (3 bit)
access : read-write
CH_SUSP : Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFG_CHx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0x0: DMA transfer from the source is not suspended 0x1: Suspend DMA transfer from the source
bits : 8 - 8 (1 bit)
access : read-write
FIFO_EMPTY : Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty
bits : 9 - 9 (1 bit)
access : read-only
HSG_SEL_DEST : Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, then this bit is ignored. 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored.
bits : 10 - 10 (1 bit)
access : read-write
HSG_SEL_SRC : Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFG_CHx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty
bits : 11 - 11 (1 bit)
access : read-write
DEST_HSG_POL : Destination Handshaking Interface Polarity. 0x0: Destination Handshaking Interface Polarity is Active high 0x1: Destination Handshaking Interface Polarity is Active low
bits : 18 - 18 (1 bit)
access : read-write
SRC_HSG_POL : Source Handshaking Interface Polarity. 0x0: Source Handshaking Interface Polarity is Active high 0x1: Source Handshaking Interface Polarity is Active low
bits : 19 - 19 (1 bit)
access : read-write
RELOAD_SRC : Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Source Reload Disabled 0x1: Source Reload Enabled
bits : 30 - 30 (1 bit)
access : read-write
RELOAD_DEST : Automatic Destination Reload. The DEST_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Destination Reload Disabled. 0x1: Destination Reload Enabled
bits : 31 - 31 (1 bit)
access : read-write
Configuration Register for Channel 6 High 32 bit
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLOW_CTRL_MODE : Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0x0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled 0x1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled.
bits : 0 - 0 (1 bit)
access : read-write
FIFO_MODE : FIFO Mode Select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0x0: Space/data available for single AHB transfer of the specified transfer width 0x1: Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer.
bits : 1 - 1 (1 bit)
access : read-write
PROT_CTRL : Protection Control bits used to drive the AHB HPROT[3:1] bus. The AMBA Specification recommends that the default of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows • 0x1 to HPROT[0] • CFGx.PROTCTL[1] to HPROT[1] • CFGx.PROTCTL[2] to HPROT[2] • CFGx.PROTCTL[3] to HPROT[3]
bits : 2 - 4 (3 bit)
access : read-write
SRC_PER : Source Hardware Interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0 otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
bits : 7 - 10 (4 bit)
access : read-write
DEST_PER : Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFGx.HSG_SEL_DST field is 0 otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
bits : 11 - 14 (4 bit)
access : read-write
Source Address for Channel 7 Low 32 bit
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_ADDR : Current Source Address of DMA transfer. Updated after each source transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true
bits : 0 - 31 (32 bit)
access : read-write
Source Address for Channel 7 High 32 bit
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register for Channel 7 Low 32 bit
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEST_ADDR : Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true
bits : 0 - 31 (32 bit)
access : read-write
Destination Address Register for Channel 7 High 32 bit
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Control Register for Channel 7 Low 32 bit
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_EN : Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel raw* interrupt registers still assert if CTRLx.INT_EN=0. 0x0: Interrupt is disabled 0x1: Interrupt is enabled Volatile: true
bits : 0 - 0 (1 bit)
access : read-write
DEST_XFE_WIDTH : Destination Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. 0x0: Destination transfer width is 8 bits 0x1: Destination transfer width is 16 bits 0x2: Destination transfer width is 32 bits Volatile: true
bits : 1 - 3 (3 bit)
access : read-write
SRC_XFE_WIDTH : Source Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. 0x0: Source transfer width is 8 bits 0x1: Source transfer width is 16 bits 0x2: Source transfer width is 32 bits Volatile: true
bits : 4 - 6 (3 bit)
access : read-write
DEST_ADDR_INC : Destination Address Increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No Change . 0x0: Increments the destination address 0x1: Decrements the destination address 0x2: No change in the destination address 0x3: No change in the destination address Volatile: true
bits : 7 - 8 (2 bit)
access : read-write
SRC_ADDR_INC : Source Address Increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change . 0x0: Increments the source address 0x1: Decrements the source address 0x2: No change in the source address 0x3: No change in the source address Volatile: true
bits : 9 - 10 (2 bit)
access : read-write
DEST_MSIZE : Destination Burst Transaction Length. Number of data items, each of width CTRL_CHx.DEST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true
bits : 11 - 13 (3 bit)
access : read-write
SRC_MSIZE : Source Burst Transaction Length. Number of data items, each of width CTRL_CHx.SRC_TR_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true
bits : 14 - 16 (3 bit)
access : read-write
XFE_TYPE_FC : Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. • 0x0: Transfer type is Memory to Memory and Flow Controller is DMA • 0x1: Transfer type is Memory to Peripheral and Flow Controller is DMA • 0x2: Transfer type is Peripheral to Memory and Flow Controller is DMA • 0x3: Transfer type is Peripheral to Peripheral and Flow Controller is DMA Volatile: true
bits : 20 - 22 (3 bit)
access : read-write
Control Register for Channel 7 High 32 bit
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLOCK_XFE_SIZE : Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_TR_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what is the flow controller. When the source or destination peripheral is assigned as the flow controller, then the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true
bits : 0 - 4 (5 bit)
access : read-write
DONE : Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx [63:32], is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer is complete. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize=2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. For more information, refer to Multi-Block Transfers . Volatile: true
bits : 12 - 12 (1 bit)
access : read-write
Configuration Register for Channel 7 Low 32 bit
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_PRIOR : Channel Priority. A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the range 0 to 3. A programmed value outside this range will cause erroneous behavior. 0x0: Channel priority is 0 0x1: Channel priority is 1 0x2: Channel priority is 2 0x3: Channel priority is 3
bits : 5 - 7 (3 bit)
access : read-write
CH_SUSP : Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFG_CHx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0x0: DMA transfer from the source is not suspended 0x1: Suspend DMA transfer from the source
bits : 8 - 8 (1 bit)
access : read-write
FIFO_EMPTY : Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty
bits : 9 - 9 (1 bit)
access : read-only
HSG_SEL_DEST : Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, then this bit is ignored. 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored.
bits : 10 - 10 (1 bit)
access : read-write
HSG_SEL_SRC : Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFG_CHx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty
bits : 11 - 11 (1 bit)
access : read-write
DEST_HSG_POL : Destination Handshaking Interface Polarity. 0x0: Destination Handshaking Interface Polarity is Active high 0x1: Destination Handshaking Interface Polarity is Active low
bits : 18 - 18 (1 bit)
access : read-write
SRC_HSG_POL : Source Handshaking Interface Polarity. 0x0: Source Handshaking Interface Polarity is Active high 0x1: Source Handshaking Interface Polarity is Active low
bits : 19 - 19 (1 bit)
access : read-write
RELOAD_SRC : Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Source Reload Disabled 0x1: Source Reload Enabled
bits : 30 - 30 (1 bit)
access : read-write
RELOAD_DEST : Automatic Destination Reload. The DEST_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Destination Reload Disabled. 0x1: Destination Reload Enabled
bits : 31 - 31 (1 bit)
access : read-write
Configuration Register for Channel 7 High 32 bit
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLOW_CTRL_MODE : Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0x0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled 0x1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled.
bits : 0 - 0 (1 bit)
access : read-write
FIFO_MODE : FIFO Mode Select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0x0: Space/data available for single AHB transfer of the specified transfer width 0x1: Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer.
bits : 1 - 1 (1 bit)
access : read-write
PROT_CTRL : Protection Control bits used to drive the AHB HPROT[3:1] bus. The AMBA Specification recommends that the default of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows • 0x1 to HPROT[0] • CFGx.PROTCTL[1] to HPROT[1] • CFGx.PROTCTL[2] to HPROT[2] • CFGx.PROTCTL[3] to HPROT[3]
bits : 2 - 4 (3 bit)
access : read-write
SRC_PER : Source Hardware Interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0 otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
bits : 7 - 10 (4 bit)
access : read-write
DEST_PER : Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFGx.HSG_SEL_DST field is 0 otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
bits : 11 - 14 (4 bit)
access : read-write
Raw Status for Transfer Complete Interrupt Low 32 bit
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAW : Raw Status for Transfer Complete Interrupt 0x0: Inactive Raw Interrupt Status 0x1: Active Raw Interrupt Status Volatile: true
bits : 0 - 3 (4 bit)
access : read-write
Raw Status for Transfer Complete Interrupt High 32 bit
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Raw Status for Block Transfer Complete Interrupt Low 32 bit
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAW : Raw Status for Block Transfer Complete Interrupt 0x0: Inactive Raw Interrupt Status 0x1: Active Raw Interrupt Status Volatile: true
bits : 0 - 3 (4 bit)
access : read-write
Raw Status for Block Transfer Complete Interrupt High 32 bit
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Raw Status for Source Transaction Complete Interrupt Low 32 bit
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAW : Raw Status for Source Transaction Complete Interrupt 0x0: Inactive Raw Interrupt Status 0x1: Active Raw Interrupt Status Volatile: true
bits : 0 - 3 (4 bit)
access : read-write
Raw Status for Source Transaction Complete Interrupt High 32 bit
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Raw Status for Destination Transaction Complete Interrupt Low 32 bit
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAW : Raw Status for Destination Transaction Complete Interrupt 0x0: Inactive Raw Interrupt Status 0x1: Active Raw Interrupt Status
bits : 0 - 3 (4 bit)
access : read-write
Raw Status for Destination Transaction Complete Interrupt High 32 bit
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Raw Status for Error Interrupt Low 32 bit
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAW : Raw Status for Error Interrupt 0x0: Inactive Raw Interrupt Status 0x1: Active Raw Interrupt Status Volatile: true
bits : 0 - 3 (4 bit)
access : read-write
Raw Status for Error Interrupt High 32 bit
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Status for Transfer Complete Interrupt Low 32 bit
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STAT : Status for Transfer Complete Interrupt 0x0: Inactive Interrupt Status 0x1: Active Interrupt Status Volatile:true
bits : 0 - 3 (4 bit)
access : read-only
Status for Transfer Complete Interrupt High 32 bit
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Status for Block Transfer Complete Interrupt Low 32 bit
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STAT : Status for Block Transfer Complete Interrupt 0x0: Inactive Interrupt Status 0x1: Active Interrupt Status Volatile: true
bits : 0 - 3 (4 bit)
access : read-only
Status for Block Transfer Complete Interrupt High 32 bit
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Status for Source Transaction Complete Interrupt Low 32 bit
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STAT : Status for Source Transaction Complete Interrupt 0x0: Inactive Interrupt Status 0x1: Active Interrupt Status Volatile: true
bits : 0 - 3 (4 bit)
access : read-only
Status for Source Transaction Complete Interrupt High 32 bit
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Status for Destination Transaction Complete Interrupt Low 32 bit
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STAT : Status for Destination Transaction Complete Interrupt 0x0: Inactive Interrupt Status 0x1: Active Interrupt Status
bits : 0 - 3 (4 bit)
access : read-only
Status for Destination Transaction Complete Interrupt High 32 bit
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Status for Error Interrupt Low 32 bit
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STAT : Status for Error Interrupt 0x0: Inactive Interrupt Status 0x1: Active Interrupt Status Volatile: true
bits : 0 - 3 (4 bit)
access : read-only
Status for Error Interrupt High 32 bit
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Mask for Transfer Complete Interrupt Low 32 bit
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_MASK : Mask for Transfer Complete Interrupt 0x0: Mask the interrupts 0x1: Unmask the interrupts
bits : 0 - 3 (4 bit)
access : read-write
INT_MASK_WE : Interrupt Mask Write Enable 0x0: Interrupt mask write disable 0x1: Interrupt mask write enable
bits : 8 - 11 (4 bit)
access : write-only
Mask for Transfer Complete Interrupt High 32 bit
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Mask for Block Transfer Complete Interrupt Low 32 bit
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_MASK : Mask for Block Transfer Complete Interrupt 0x0: Mask the interrupts 0x1: Unmask the interrupts
bits : 0 - 3 (4 bit)
access : read-write
INT_MASK_WE : Interrupt Mask Write Enable 0x0: Interrupt mask write disable 0x1: Interrupt mask write enable
bits : 8 - 11 (4 bit)
access : write-only
Mask for Block Transfer Complete Interrupt High 32 bit
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Mask for Source Transaction Complete Interrupt Low 32 bit
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_MASK : Mask for Source Transaction Complete Interrupt 0x0: Mask the interrupts 0x1: Unmask the interrupts
bits : 0 - 3 (4 bit)
access : read-write
INT_MASK_WE : Interrupt Mask Write Enable 0x0: Interrupt mask write disable 0x1: Interrupt mask write enable
bits : 8 - 11 (4 bit)
access : write-only
Mask for Source Transaction Complete Interrupt High 32 bit
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Mask for Destination Transaction Complete Interrupt Low 32 bit
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_MASK : Mask for Destination Transaction Complete Interrupt 0x0: Mask the interrupts 0x1: Unmask the interrupts
bits : 0 - 3 (4 bit)
access : read-write
INT_MASK_WE : Interrupt Mask Write Enable 0x0: Interrupt mask write disable 0x1: Interrupt mask write enable
bits : 8 - 11 (4 bit)
access : write-only
Mask for Destination Transaction Complete Interrupt High 32 bit
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Mask for Error Interrupt Low 32 bit
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_MASK : Mask for Error Interrupt 0x0: Mask the interrupts 0x1: Unmask the interrupts
bits : 0 - 3 (4 bit)
access : read-write
INT_MASK_WE : Interrupt Mask Write Enable 0x0: Interrupt mask write disable 0x1: Interrupt mask write enable
bits : 8 - 11 (4 bit)
access : write-only
Mask for Error Interrupt High 32 bit
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Clear for Transfer Complete Interrupt Low 32 bit
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR : Clear for Transfer Complete Interrupt 0x0: No effect 0x1: Clears interrupts Volatile: true
bits : 0 - 3 (4 bit)
access : write-only
Clear for Transfer Complete Interrupt High 32 bit
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Clear for Block Transfer Complete Interrupt Low 32 bit
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR : Clear for Block Transfer Complete Interrupt Volatile: true
bits : 0 - 3 (4 bit)
access : write-only
Clear for Block Transfer Complete Interrupt High 32 bit
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Clear for Source Transaction Complete Interrupt Low 32 bit
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR : Clear for Source Transaction Complete Interrupt 0x0: No effect 0x1: Clears interrupts Volatile: true
bits : 0 - 3 (4 bit)
access : write-only
Clear for Source Transaction Complete Interrupt High 32 bit
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Clear for Destination Transaction Complete Interrupt Low 32 bit
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR : Clear for Destination Transaction Complete Interrupt 0x0: No effect 0x1: Clears interrupts Volatile: true
bits : 0 - 3 (4 bit)
access : write-only
Clear for Destination Transaction Complete Interrupt High 32 bit
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Clear for Error Interrupt Low 32 bit
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR : Clear for Error Interrupt 0x0: No effect 0x1: Clears interrupts Volatile: true
bits : 0 - 3 (4 bit)
access : write-only
Clear for Error Interrupt High 32 bit
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Status for each Interrupt type Low 32 bit
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
XFE_CPLT : OR of the contents of INT_STAT_TC register 0x0: OR of the contents of INT_STAT_TC register is 0 0x1: OR of the contents of INT_STAT_TC register is 1 Volatile: true
bits : 0 - 0 (1 bit)
access : read-only
BLK_XFE_CPLT : OR of the contents of INT_STAT_BTC register 0x0: OR of the contents of INT_STAT_BTC register is 0 0x1: OR of the contents of INT_STAT_BTC register is 1 Volatile: true
bits : 1 - 1 (1 bit)
access : read-only
SRC_XFE_CPLT : OR of the contents of INT_STAT_STC register 0x0: OR of the contents of INT_STAT_STC register is 0 0x1: OR of the contents of INT_STAT_STC register is 1 Volatile: true
bits : 2 - 2 (1 bit)
access : read-only
DEST_XFE_CPLT : OR of the contents of INT_STAT_DTC register 0x0: OR of the contents of INT_STAT_DTC register is 0 0x1: OR of the contents of INT_STAT_DTC register is 1 Volatile: true
bits : 3 - 3 (1 bit)
access : read-only
ERR : OR of the contents of INT_STAT_ERR register 0x0: OR of the contents of INT_STAT_ERR register is 0 0x1: OR of the contents of INT_STAT_ERR register is 1 Volatile: true
bits : 4 - 4 (1 bit)
access : read-only
Status for each Interrupt type High 32 bit
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Software Transaction Request register Low 32 bit
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_REQ : Source Software Transaction Request 0x0: Source request is not active 0x1: Source request is active
bits : 0 - 3 (4 bit)
access : read-write
SRC_REQ_WE : Source Software Transaction Request write enable 0x0: Source request write Disable 0x1: Source request write Enable
bits : 8 - 11 (4 bit)
access : read-write
Source Software Transaction Request register High 32 bit
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Software Transaction Request register Low 32 bit
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEST_REQ : Destination Software Transaction Request 0x0: Destination request is not active 0x1: Destination request is active
bits : 0 - 3 (4 bit)
access : read-write
DEST_REQ_WE : Destination Software Transaction Request write enable 0x0: Destination request write Disable 0x1: Destination request write Enable
bits : 8 - 11 (4 bit)
access : read-write
Destination Software Transaction Request register High 32 bit
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Single Transaction Request register Low 32 bit
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_SGL_REQ : Source Single Transaction Request 0x0: Source request is not active 0x1: Source request is active
bits : 0 - 3 (4 bit)
access : read-write
SRC_SGL_REQ_WE : Source Single Transaction Request write enable 0x0: Single write Disable 0x1: Single write Enable
bits : 8 - 11 (4 bit)
access : read-write
Source Single Transaction Request register High 32 bit
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Single Transaction Request register Low 32 bit
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEST_SGL_REQ : Destination Single Transaction Request 0x0: Destination Single or burst request is not active 0x1: Destination Single or burst request is active
bits : 0 - 3 (4 bit)
access : read-write
DST_SGL_REQ_WE : Destination Single Transaction Request write enable 0x0: Destination write Disable 0x1: Destination write Enable
bits : 8 - 11 (4 bit)
access : read-write
Destination Single Transaction Request register High 32 bit
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Last Transaction Request register Low 32 bit
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LST_SRC : Source Last Transaction Request register 0x0: Not last transaction in current block 0x1: Last transaction in current block
bits : 0 - 3 (4 bit)
access : read-write
LST_SRC_WE : Source Last Transaction Request write enable 0x0: Source last transaction request write disable 0x1: Source last transaction request write enable
bits : 8 - 11 (4 bit)
access : read-write
Source Last Transaction Request register High 32 bit
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Last Transaction Request register Low 32 bit
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LST_DEST : Destination Last Transaction Request 0x0: Not last transaction in current block 0x1: Last transaction in current block
bits : 0 - 3 (4 bit)
access : read-write
LST_DEST_WE : Source Last Transaction Request write enable 0x0: Destination last transaction request write disable 0x1: Destination last transaction request write enable
bits : 8 - 11 (4 bit)
access : read-write
Destination Last Transaction Request register High 32 bit
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Configuration Register Low 32 bit
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_EN : DMA Enable bit. 0x0: DMA Disabled 0x1: DMA Enabled Volatile: true
bits : 0 - 0 (1 bit)
access : read-write
DMA Configuration Register High 32 bit
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Channel Enable Register Low 32 bit
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_EN : Channel Enable. The CH_EN.CH_EN bit is automatically cleared by hardware to disable the channel after the last AMBA transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer. 0x0: Disable the channel 0x1: Enable the channel Volatile: true
bits : 0 - 3 (4 bit)
access : read-write
CH_EN_WE : Channel enable register Volatile: true
bits : 8 - 11 (4 bit)
access : write-only
DMA Channel Enable Register High 32 bit
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address for Channel 0 High 32 bit
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configuration Register for Channel 0 Low 32 bit
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_PRIOR : Channel Priority. A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the range 0 to 3. A programmed value outside this range will cause erroneous behavior. 0x0: Channel priority is 0 0x1: Channel priority is 1 0x2: Channel priority is 2 0x3: Channel priority is 3
bits : 5 - 7 (3 bit)
access : read-write
CH_SUSP : Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFG_CHx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0x0: DMA transfer from the source is not suspended 0x1: Suspend DMA transfer from the source
bits : 8 - 8 (1 bit)
access : read-write
FIFO_EMPTY : Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty
bits : 9 - 9 (1 bit)
access : read-only
HSG_SEL_DEST : Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, then this bit is ignored. 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored.
bits : 10 - 10 (1 bit)
access : read-write
HSG_SEL_SRC : Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFG_CHx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty
bits : 11 - 11 (1 bit)
access : read-write
DEST_HSG_POL : Destination Handshaking Interface Polarity. 0x0: Destination Handshaking Interface Polarity is Active high 0x1: Destination Handshaking Interface Polarity is Active low
bits : 18 - 18 (1 bit)
access : read-write
SRC_HSG_POL : Source Handshaking Interface Polarity. 0x0: Source Handshaking Interface Polarity is Active high 0x1: Source Handshaking Interface Polarity is Active low
bits : 19 - 19 (1 bit)
access : read-write
RELOAD_SRC : Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Source Reload Disabled 0x1: Source Reload Enabled
bits : 30 - 30 (1 bit)
access : read-write
RELOAD_DEST : Automatic Destination Reload. The DEST_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Destination Reload Disabled. 0x1: Destination Reload Enabled
bits : 31 - 31 (1 bit)
access : read-write
Configuration Register for Channel 0 High 32 bit
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLOW_CTRL_MODE : Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0x0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled 0x1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled.
bits : 0 - 0 (1 bit)
access : read-write
FIFO_MODE : FIFO Mode Select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0x0: Space/data available for single AHB transfer of the specified transfer width 0x1: Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer.
bits : 1 - 1 (1 bit)
access : read-write
PROT_CTRL : Protection Control bits used to drive the AHB HPROT[3:1] bus. The AMBA Specification recommends that the default of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows: • 0x1 to HPROT[0] • CFGx.PROTCTL[1] to HPROT[1] • CFGx.PROTCTL[2] to HPROT[2] • CFGx.PROTCTL[3] to HPROT[3]
bits : 2 - 4 (3 bit)
access : read-write
SRC_PER : Source Hardware Interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0 otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
bits : 7 - 10 (4 bit)
access : read-write
DEST_PER : Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFGx.HSG_SEL_DST field is 0 otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
bits : 11 - 14 (4 bit)
access : read-write
Source Address for Channel 1 LOW 32 bit
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_ADDR : Current Source Address of DMA transfer. Updated after each source transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true
bits : 0 - 31 (32 bit)
access : read-write
Source Address for Channel 1 High 32 bit
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register for Channel 1 Low 32 bit
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEST_ADDR : Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true
bits : 0 - 31 (32 bit)
access : read-write
Destination Address Register for Channel 1 High 32 bit
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Control Register for Channel 1 Low 32 bit
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_EN : Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel raw* interrupt registers still assert if CTRLx.INT_EN=0. 0x0: Interrupt is disabled 0x1: Interrupt is enabled Volatile: true
bits : 0 - 0 (1 bit)
access : read-write
DEST_XFE_WIDTH : Destination Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. 0x0: Destination transfer width is 8 bits 0x1: Destination transfer width is 16 bits 0x2: Destination transfer width is 32 bits Volatile: true
bits : 1 - 3 (3 bit)
access : read-write
SRC_XFE_WIDTH : Source Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. 0x0: Source transfer width is 8 bits 0x1: Source transfer width is 16 bits 0x2: Source transfer width is 32 bits Volatile: true
bits : 4 - 6 (3 bit)
access : read-write
DEST_ADDR_INC : Destination Address Increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No Change . 0x0: Increments the destination address 0x1: Decrements the destination address 0x2: No change in the destination address 0x3: No change in the destination address Volatile: true
bits : 7 - 8 (2 bit)
access : read-write
SRC_ADDR_INC : Source Address Increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change . 0x0: Increments the source address 0x1: Decrements the source address 0x2: No change in the source address 0x3: No change in the source address Volatile: true
bits : 9 - 10 (2 bit)
access : read-write
DEST_MSIZE : Destination Burst Transaction Length. Number of data items, each of width CTRL_CHx.DEST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true
bits : 11 - 13 (3 bit)
access : read-write
SRC_MSIZE : Source Burst Transaction Length. Number of data items, each of width CTRL_CHx.SRC_TR_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true
bits : 14 - 16 (3 bit)
access : read-write
XFE_TYPE_FC : Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. • 0x0: Transfer type is Memory to Memory and Flow Controller is DMA • 0x1: Transfer type is Memory to Peripheral and Flow Controller is DMA • 0x2: Transfer type is Peripheral to Memory and Flow Controller is DMA • 0x3: Transfer type is Peripheral to Peripheral and Flow Controller is DMA Volatile: true
bits : 20 - 22 (3 bit)
access : read-write
Control Register for Channel 1 High 32 bit
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLOCK_XFE_SIZE : Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_TR_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what is the flow controller. When the source or destination peripheral is assigned as the flow controller, then the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true
bits : 0 - 4 (5 bit)
access : read-write
DONE : Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx [63:32], is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer is complete. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize=2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. For more information, refer to Multi-Block Transfers . Volatile: true
bits : 12 - 12 (1 bit)
access : read-write
Destination Address Register for Channel 0 Low 32 bit
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEST_ADDR : Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true
bits : 0 - 31 (32 bit)
access : read-write
Configuration Register for Channel 1 Low 32 bit
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_PRIOR : Channel Priority. A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the range 0 to 3. A programmed value outside this range will cause erroneous behavior. 0x0: Channel priority is 0 0x1: Channel priority is 1 0x2: Channel priority is 2 0x3: Channel priority is 3
bits : 5 - 7 (3 bit)
access : read-write
CH_SUSP : Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFG_CHx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0x0: DMA transfer from the source is not suspended 0x1: Suspend DMA transfer from the source
bits : 8 - 8 (1 bit)
access : read-write
FIFO_EMPTY : Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty
bits : 9 - 9 (1 bit)
access : read-only
HSG_SEL_DEST : Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, then this bit is ignored. 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored.
bits : 10 - 10 (1 bit)
access : read-write
HSG_SEL_SRC : Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFG_CHx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty
bits : 11 - 11 (1 bit)
access : read-write
DEST_HSG_POL : Destination Handshaking Interface Polarity. 0x0: Destination Handshaking Interface Polarity is Active high 0x1: Destination Handshaking Interface Polarity is Active low
bits : 18 - 18 (1 bit)
access : read-write
SRC_HSG_POL : Source Handshaking Interface Polarity. 0x0: Source Handshaking Interface Polarity is Active high 0x1: Source Handshaking Interface Polarity is Active low
bits : 19 - 19 (1 bit)
access : read-write
RELOAD_SRC : Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Source Reload Disabled 0x1: Source Reload Enabled
bits : 30 - 30 (1 bit)
access : read-write
RELOAD_DEST : Automatic Destination Reload. The DEST_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Destination Reload Disabled. 0x1: Destination Reload Enabled
bits : 31 - 31 (1 bit)
access : read-write
Configuration Register for Channel 1 High 32 bit
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLOW_CTRL_MODE : Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0x0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled 0x1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled.
bits : 0 - 0 (1 bit)
access : read-write
FIFO_MODE : FIFO Mode Select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0x0: Space/data available for single AHB transfer of the specified transfer width 0x1: Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer.
bits : 1 - 1 (1 bit)
access : read-write
PROT_CTRL : Protection Control bits used to drive the AHB HPROT[3:1] bus. The AMBA Specification recommends that the default of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows: • 0x1 to HPROT[0] • CFGx.PROTCTL[1] to HPROT[1] • CFGx.PROTCTL[2] to HPROT[2] • CFGx.PROTCTL[3] to HPROT[3]
bits : 2 - 4 (3 bit)
access : read-write
SRC_PER : Source Hardware Interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0 otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
bits : 7 - 10 (4 bit)
access : read-write
DEST_PER : Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFGx.HSG_SEL_DST field is 0 otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
bits : 11 - 14 (4 bit)
access : read-write
Source Address for Channel 2 LOW 32 bit
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_ADDR : Current Source Address of DMA transfer. Updated after each source transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true
bits : 0 - 31 (32 bit)
access : read-write
Source Address for Channel 2 High 32 bit
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register for Channel 2 Low 32 bit
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEST_ADDR : Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true
bits : 0 - 31 (32 bit)
access : read-write
Destination Address Register for Channel 2 High 32 bit
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register for Channel 0 High 32 bit
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Control Register for Channel 2 Low 32 bit
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_EN : Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel raw* interrupt registers still assert if CTRLx.INT_EN=0. 0x0: Interrupt is disabled 0x1: Interrupt is enabled Volatile: true
bits : 0 - 0 (1 bit)
access : read-write
DEST_XFE_WIDTH : Destination Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. 0x0: Destination transfer width is 8 bits 0x1: Destination transfer width is 16 bits 0x2: Destination transfer width is 32 bits Volatile: true
bits : 1 - 3 (3 bit)
access : read-write
SRC_XFE_WIDTH : Source Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. 0x0: Source transfer width is 8 bits 0x1: Source transfer width is 16 bits 0x2: Source transfer width is 32 bits Volatile: true
bits : 4 - 6 (3 bit)
access : read-write
DEST_ADDR_INC : Destination Address Increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No Change . 0x0: Increments the destination address 0x1: Decrements the destination address 0x2: No change in the destination address 0x3: No change in the destination address Volatile: true
bits : 7 - 8 (2 bit)
access : read-write
SRC_ADDR_INC : Source Address Increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change . 0x0: Increments the source address 0x1: Decrements the source address 0x2: No change in the source address 0x3: No change in the source address Volatile: true
bits : 9 - 10 (2 bit)
access : read-write
DEST_MSIZE : Destination Burst Transaction Length. Number of data items, each of width CTRL_CHx.DEST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true
bits : 11 - 13 (3 bit)
access : read-write
SRC_MSIZE : Source Burst Transaction Length. Number of data items, each of width CTRL_CHx.SRC_TR_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true
bits : 14 - 16 (3 bit)
access : read-write
XFE_TYPE_FC : Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. • 0x0: Transfer type is Memory to Memory and Flow Controller is DMA • 0x1: Transfer type is Memory to Peripheral and Flow Controller is DMA • 0x2: Transfer type is Peripheral to Memory and Flow Controller is DMA • 0x3: Transfer type is Peripheral to Peripheral and Flow Controller is DMA Volatile: true
bits : 20 - 22 (3 bit)
access : read-write
Control Register for Channel 2 High 32 bit
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLOCK_XFE_SIZE : Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_TR_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what is the flow controller. When the source or destination peripheral is assigned as the flow controller, then the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true
bits : 0 - 4 (5 bit)
access : read-write
DONE : Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx [63:32], is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer is complete. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize=2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. For more information, refer to Multi-Block Transfers . Volatile: true
bits : 12 - 12 (1 bit)
access : read-write
Configuration Register for Channel 2 Low 32 bit
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_PRIOR : Channel Priority. A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the range 0 to 3. A programmed value outside this range will cause erroneous behavior. 0x0: Channel priority is 0 0x1: Channel priority is 1 0x2: Channel priority is 2 0x3: Channel priority is 3
bits : 5 - 7 (3 bit)
access : read-write
CH_SUSP : Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFG_CHx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0x0: DMA transfer from the source is not suspended 0x1: Suspend DMA transfer from the source
bits : 8 - 8 (1 bit)
access : read-write
FIFO_EMPTY : Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty
bits : 9 - 9 (1 bit)
access : read-only
HSG_SEL_DEST : Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, then this bit is ignored. 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored.
bits : 10 - 10 (1 bit)
access : read-write
HSG_SEL_SRC : Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFG_CHx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty
bits : 11 - 11 (1 bit)
access : read-write
DEST_HSG_POL : Destination Handshaking Interface Polarity. 0x0: Destination Handshaking Interface Polarity is Active high 0x1: Destination Handshaking Interface Polarity is Active low
bits : 18 - 18 (1 bit)
access : read-write
SRC_HSG_POL : Source Handshaking Interface Polarity. 0x0: Source Handshaking Interface Polarity is Active high 0x1: Source Handshaking Interface Polarity is Active low
bits : 19 - 19 (1 bit)
access : read-write
RELOAD_SRC : Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Source Reload Disabled 0x1: Source Reload Enabled
bits : 30 - 30 (1 bit)
access : read-write
RELOAD_DEST : Automatic Destination Reload. The DEST_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Destination Reload Disabled. 0x1: Destination Reload Enabled
bits : 31 - 31 (1 bit)
access : read-write
Configuration Register for Channel 2 High 32 bit
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLOW_CTRL_MODE : Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0x0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled 0x1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled.
bits : 0 - 0 (1 bit)
access : read-write
FIFO_MODE : FIFO Mode Select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0x0: Space/data available for single AHB transfer of the specified transfer width 0x1: Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer.
bits : 1 - 1 (1 bit)
access : read-write
PROT_CTRL : Protection Control bits used to drive the AHB HPROT[3:1] bus. The AMBA Specification recommends that the default of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows: • 0x1 to HPROT[0] • CFGx.PROTCTL[1] to HPROT[1] • CFGx.PROTCTL[2] to HPROT[2] • CFGx.PROTCTL[3] to HPROT[3]
bits : 2 - 4 (3 bit)
access : read-write
SRC_PER : Source Hardware Interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0 otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
bits : 7 - 10 (4 bit)
access : read-write
DEST_PER : Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFGx.HSG_SEL_DST field is 0 otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
bits : 11 - 14 (4 bit)
access : read-write
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