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HMAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x6C byte (0x0)
mem_usage : registers
protection :

Registers

CTRL

INT

RD_START_ADDR

WR_START_ADDR

USER_HASH_0

USER_HASH_1

USER_HASH_2

USER_HASH_3

USER_HASH_4

USER_HASH_5

USER_HASH_6

USER_HASH_7

CFG

DATA_OUT

DATA_IN

KEY0

KEY1

KEY2

KEY3

KEY4

KEY5

KEY6

KEY7

KEY_ADDR

KEYPORT_MASK

STAT

XFE_SIZE


CTRL

HMAC Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMA_START KEY_EN LST_TX

EN : HMAC enable, high valid for whole HMAC processing, user must disable it once all block HMAC completes. This signal should be asserted until all blocks completes
bits : 0 - 0 (1 bit)
access : read-write

DMA_START : DMA mode start enable. Starting DMA transfer, this signal should be cleared after DMA have finished all transfer
bits : 1 - 1 (1 bit)
access : read-write

KEY_EN : Enable HMAC fetch key by itself through AHB master interface or key port. This signal may be cleared by itself when aes_key_valid was set
bits : 2 - 2 (1 bit)
access : write-only

LST_TX : Last block in MCU model or last DMA transfer. This signal may be cleared by itself when hmac_ready was set
bits : 3 - 3 (1 bit)
access : write-only


INT

HMAC Interrupt Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DONE EN

DONE : HMAC result data complete interrupt flag. Write 1 to clear. Read 0x0: Not interrupt 0x1: Interrupt Write 0x0: Not effect 0x1: Clear
bits : 0 - 0 (1 bit)
access : read-write

EN : HMAC result data complete interrupt enable. 0x0: Disable 0x1: Enable
bits : 1 - 1 (1 bit)
access : read-write


RD_START_ADDR

HMAC Read Start Address Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RD_START_ADDR RD_START_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : DMA mode, read start address of transfer
bits : 0 - 31 (32 bit)
access : read-write


WR_START_ADDR

HMAC Write Start Address Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WR_START_ADDR WR_START_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : DMA mode, write start address of transfer
bits : 0 - 31 (32 bit)
access : read-write


USER_HASH_0

HMAC User Hash 0 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER_HASH_0 USER_HASH_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_0

HASH_0 : If HASH is selected, you can configure user defined hash with USER_HASH_0 /1/2/3/4/5/6/7. User defined hash value[255:224]
bits : 0 - 31 (32 bit)
access : read-write


USER_HASH_1

HMAC User Hash 1 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER_HASH_1 USER_HASH_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_1

HASH_1 : If HASH is selected, you can configure user defined hash with USER_HASH_0/1/2/3/4/5/6/7. User defined hash value[223:192]
bits : 0 - 31 (32 bit)
access : read-write


USER_HASH_2

HMAC User Hash 2 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER_HASH_2 USER_HASH_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_2

HASH_2 : If HASH is selected, you can configure user defined hash with USER_HASH_0 /1/2/3/4/5/6/7. User defined hash value[191:160]
bits : 0 - 31 (32 bit)
access : read-write


USER_HASH_3

HMAC User Hash 3 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER_HASH_3 USER_HASH_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_3

HASH_3 : If HASH is selected, you can configure user defined hash with USER_HASH_0 /1/2/3/4/5/6/7. User defined hash value[159:128]
bits : 0 - 31 (32 bit)
access : read-write


USER_HASH_4

HMAC User Hash 4 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER_HASH_4 USER_HASH_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_4

HASH_4 : If HASH is selected, you can configure user defined hash with USER_HASH_0 /1/2/3/4/5/6/7. User defined hash value[127:96]
bits : 0 - 31 (32 bit)
access : read-write


USER_HASH_5

HMAC User Hash 5 Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER_HASH_5 USER_HASH_5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_5

HASH_5 : If HASH is selected, you can configure user defined hash with USER_HASH_0 /1/2/3/4/5/6/7. User defined hash value[95:64]
bits : 0 - 31 (32 bit)
access : read-write


USER_HASH_6

HMAC User Hash 6 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER_HASH_6 USER_HASH_6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_6

HASH_6 : If HASH is selected, you can configure user defined hash with USER_HASH_0 /1/2/3/4/5/6/7. User defined hash value[63:32]
bits : 0 - 31 (32 bit)
access : read-write


USER_HASH_7

HMAC User Hash 7 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER_HASH_7 USER_HASH_7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_7

HASH_7 : If HASH is selected, you can configure user defined hash with USER_HASH_0 /1/2/3/4/5/6/7. User defined hash value[31:0]
bits : 0 - 31 (32 bit)
access : read-write


CFG

HMAC Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH ENDIAN KEY_TYPE CALC_TYPE PRIVT_MOD

HASH : Select enable for user define hash 0x0: initial hash from standard(default) 0x1: user defined initial hash enable
bits : 0 - 0 (1 bit)
access : read-write

ENDIAN : Selection for endian ctrl 0x0: Reverse to big_endian(default) 0x1: No reverse
bits : 1 - 1 (1 bit)
access : read-write

KEY_TYPE : Select key type 0x0: Configured by MCU 0x1: Fetched through AHB interface 0x2: Fetched through key port 0x3: Reserved
bits : 2 - 3 (2 bit)
access : read-write

CALC_TYPE : Select calculation type 0x0: HMAC 0x1: SHA
bits : 4 - 4 (1 bit)
access : read-write

PRIVT_MOD : To resist DPA, need to select private mode 0x0: Standard mode 0x1: Private mode
bits : 5 - 5 (1 bit)
access : read-write


DATA_OUT

HMAC Data Output Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DATA_OUT DATA_OUT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : MCU mode, user can read out result with this register: When all blocks of message were processed, 256 bit HMAC data should be read out 8/9 times. And HMAC data can be read when hmac_ready is valid.
bits : 0 - 31 (32 bit)
access : read-only


DATA_IN

HMAC Data Input Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DATA_IN DATA_IN write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : MCU mode, user can configure input data with this register: 32-bit data should be sent 16/17 times.
bits : 0 - 31 (32 bit)
access : write-only


KEY0

HMAC Key 0 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY0 KEY0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY0

KEY0 : Key was set as 256 bits (8 WORDs ), WORD_0
bits : 0 - 31 (32 bit)
access : write-only


KEY1

HMAC Key 1 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY1 KEY1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY1

KEY1 : Key was set as 256 bits (8 WORDs ), WORD_1
bits : 0 - 31 (32 bit)
access : write-only


KEY2

HMAC Key 2 Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY2 KEY2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY2

KEY2 : Key was set as 256 bits (8 WORDs ), WORD_2
bits : 0 - 31 (32 bit)
access : write-only


KEY3

HMAC Key 3 Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY3 KEY3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY3

KEY3 : Key was set as 256 bits (8 WORDs ), WORD_3
bits : 0 - 31 (32 bit)
access : write-only


KEY4

HMAC Key 4 Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY4 KEY4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY4

KEY4 : Key was set as 256 bits (8 WORDs ), WORD_4
bits : 0 - 31 (32 bit)
access : write-only


KEY5

HMAC Key 5 Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY5 KEY5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY5

KEY5 : Key was set as 256 bits (8 WORDs ), WORD_5
bits : 0 - 31 (32 bit)
access : write-only


KEY6

HMAC Key 6 Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY6 KEY6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY6

KEY6 : Key was set as 256 bits (8 WORDs ), WORD_6
bits : 0 - 31 (32 bit)
access : write-only


KEY7

HMAC Key 7 Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY7 KEY7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY7

KEY7 : Key was set as 256 bits (8 WORDs ), WORD_7
bits : 0 - 31 (32 bit)
access : write-only


KEY_ADDR

HMAC Key Addr Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEY_ADDR KEY_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY_ADDR

KEY_ADDR : HMAC key address in memory
bits : 0 - 31 (32 bit)
access : read-write


KEYPORT_MASK

HMAC Keyport Mask Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYPORT_MASK KEYPORT_MASK write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Mask for key from keyport
bits : 0 - 31 (32 bit)
access : write-only


STAT

HMAC Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_READY DMA_MSG_DONE DMA_TX_ERR KEY_VALID HMAC_READY DMA_TX_DONE

HASH_READY : Hash process status 0x0: Result data is not ready 0x1: Result data is valid
bits : 0 - 0 (1 bit)
access : read-only

DMA_MSG_DONE : If the number of all block message bigger than transfer size, it indicates all block message was sent when this signal was set
bits : 1 - 1 (1 bit)
access : read-only

DMA_TX_ERR : HMAC DMA transfer error. Write 1 to clear
bits : 2 - 2 (1 bit)
access : read-write

KEY_VALID : Hmac has fetched key or not
bits : 3 - 3 (1 bit)
access : read-only

HMAC_READY : HMAC process status 0x0: Result data is not ready 0x1: Result data is valid
bits : 4 - 4 (1 bit)
access : read-write

DMA_TX_DONE : HMAC dma transfer done or not
bits : 5 - 5 (1 bit)
access : read-write


XFE_SIZE

HMAC Transfer Size Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XFE_SIZE XFE_SIZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE

SIZE : Total transfer size, up to 32KB 0x003F: 1 block 0x007F: 2 block 0x00BF: 3 block - 0x7FFF: 512 block
bits : 0 - 14 (15 bit)
access : read-write



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