CTRL

DATA_CMD

SS_CLK_HCOUNT

SS_CLK_LCOUNT

FS_CLK_HCOUNT

FS_CLK_LCOUNT

HS_CLK_HCOUNT

HS_CLK_LCOUNT

INT_STAT

INT_MASK

RAW_INT_STAT

RX_FIFO_THD

TX_FIFO_THD

TARGET_ADDR

CLR_INT

CLR_RX_UNDER

CLR_RX_OVER

CLR_TX_OVER

CLR_RD_REQ

CLR_TX_ABORT

CLR_RX_DONE

CLR_ACTIVITY

CLR_STOP_DET

CLR_START_DET

CLR_GEN_CALL

EN

STAT

TX_FIFO_LEVEL

RX_FIFO_LEVEL

SDA_HOLD

S_ADDR

TX_ABORT_SRC

DMA_CTRL

DMA_TX_LEVEL

DMA_RX_LEVEL

SDA_SETUP

ACK_GEN_CALL

EN_STAT

FS_SPKLEN

HS_SPKLEN

M_HS_ADDR

M_MODE : This bit controls whether the I2C master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. 0x0: Master mode is disabled 0x1: Master mode is enabled
bits : 0 - 0 (1 bit)
access : read-write

SPEED : These bits control at which speed the I2C operates its setting is relevant only if one is operating the I2C in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to 3. 0x1: Standard Speed mode of operation(100 kbit/s) 0x2: Fast( ≤400 kbit/s) or Fast Plus(≤1000Kbit/s) mode of operation 0x3: High Speed mode of operation(3.4 Mbit/s)
bits : 1 - 2 (2 bit)
access : read-write

ADDR_BIT_S : When acting as a slave, this bit controls whether the I2C responds to 7- or 10-bit addresses. 0x0: Slave 7Bit addressing 0x1: Slave 10Bit addressing
bits : 3 - 3 (1 bit)
access : read-write

ADDR_BIT_M : When acting as a master, this bit controls whether the I2C starts its transfers in 7-bit or 10-bit addressing mode. 0x0: Master 7Bit addressing mode 0x1: Master 10Bit addressing mode
bits : 4 - 4 (1 bit)
access : read-write

RESTART_EN : Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions however, RESTART conditions are used in several I2C operations. When RESTART is disabled, the master is prohibited from performing the following functions: • Sending a START BYTE • Performing any high-speed mode operation • High-speed mode operation • Performing direction changes in combined format mode • Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple I2C transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABORT) of the RAW_INTR_STAT register. 0x0: Master restart disabled 0x1: Master restart enabled
bits : 5 - 5 (1 bit)
access : read-write

S_DIS : This bit controls whether I2C has its slave disabled. By default, the slave is always disabled (in reset state as well). If you need to enable it after reset, set this bit to 0. If this bit is set (slave is disabled), I2C functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. Value: 0x0: Slave mode is enabled 0x1: Slave mode is disabled
bits : 6 - 6 (1 bit)
access : read-write

STOP_DET_INT : In slave mode 0x0: Issues the STOP_DET irrespective of whether it's addressed or not 0x1: Issues the STOP_DET interrrupt only when it is addressed NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_INT = 1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (S_ADDR). 0x0: Slave issues STOP_DET intr always 0x1: Slave issues STOP_DET intr only if addressed
bits : 7 - 7 (1 bit)
access : read-write

TX_EMPTY_CTRL : This bit controls the generation of the TX_EMPTY interrupt, as described in the RAW_INTR_STAT register. 0x0: Default disable behaviour of TX_EMPTY interrupt 0x1: Controlled enable generation of TX_EMPTY interrupt
bits : 8 - 8 (1 bit)
access : read-write

STOP_DET_M_ACTIVE : In Master mode 0x1: issues the STOP_DET interrupt only when master is active. 0x0: issues the STOP_DET irrespective of whether master is active or not. 0x1: Master issues the STOP_DET interrupt only when master is active 0x0: Master issues the STOP_DET interrupt irrespective of whether master is active or not
bits : 10 - 10 (1 bit)
access : read-write

DATA : This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DATA) are ignored by the I2C. However, when you read this register, these bits return the value of data received on the I2C interface.
bits : 0 - 7 (8 bit)
access : read-write

CMD : This bit controls whether a read or a write is performed. This bit does not control the direction when the I2C acts as a slave. It controls only the direction when it acts as a master. 0x0: Master Write command 0x1: Master Read command
bits : 8 - 8 (1 bit)
access : read-write

COUNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set. NOTE: This register must not be programmed to a value higher than 65525, because I2C uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of COUNT + 10.
bits : 0 - 15 (16 bit)
access : read-write

COUNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted, results in 8 being set.
bits : 0 - 15 (16 bit)
access : read-write

COUNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set.
bits : 0 - 15 (16 bit)
access : read-write

COUNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted results in 8 being set.
bits : 0 - 15 (16 bit)
access : read-write

COUNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. The SCL High time depends on the loading of the bus. For 100pF loading, the SCL High time is 60ns for 400pF loading, the SCL High time is 120ns. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set.
bits : 0 - 15 (16 bit)
access : read-write

COUNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. The SCL low time depends on the loading of the bus. For 100pF loading, the SCL low time is 160ns for 400pF loading, the SCL low time is 320ns. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect.
bits : 0 - 15 (16 bit)
access : read-write

RAW_RX_UNDER : See RAW_INT_STAT for a detailed description of RX_UNDER bit. 0x0: RAW_RX_UNDER interrupt is inactive 0x1: RAW_RX_UNDER interrupt is active
bits : 0 - 0 (1 bit)
access : read-only

RAW_RX_OVER : See RAW_INT_STAT for a detailed description of RX_OVER bit. 0x0: RAW_RX_OVER interrupt is inactive 0x1: RAW_RX_OVER interrupt is active
bits : 1 - 1 (1 bit)
access : read-only

RAW_RX_FULL : See RAW_INT_STAT for a detailed description of RX_FULL bit. 0x0: RAW_RX_FULL interrupt is inactive 0x1: RAW_RX_FULL interrupt is active
bits : 2 - 2 (1 bit)
access : read-only

RAW_TX_OVER : See RAW_INT_STAT for a detailed description of TX_OVER bit. 0x0: RAW_TX_OVER interrupt is inactive 0x1: RAW_TX_OVER interrupt is active
bits : 3 - 3 (1 bit)
access : read-only

RAW_TX_EMPTY : See RAW_INT_STAT for a detailed description of TX_EMPTY bit. 0x0: RAW_TX_EMPTY interrupt is inactive 0x1: RAW_TX_EMPTY interrupt is active
bits : 4 - 4 (1 bit)
access : read-only

RAW_RD_REQ : See RAW_INT_STAT for a detailed description of RD_REQ bit. 0x0: RAW_RD_REQ interrupt is inactive 0x1: RAW_RD_REQ interrupt is active
bits : 5 - 5 (1 bit)
access : read-only

RAW_TX_ABORT : See RAW_INT_STAT for a detailed description of TX_ABORT bit. 0x0: RAW_TX_ABORT interrupt is inactive 0x1: RAW_TX_ABORT interrupt is active
bits : 6 - 6 (1 bit)
access : read-only

RAW_RX_DONE : See RAW_INT_STAT for a detailed description of RX_DONE bit. 0x0: RAW_RX_DONE interrupt is inactive 0x1: RAW_RX_DONE interrupt is active
bits : 7 - 7 (1 bit)
access : read-only

RAW_ACTIVITY : See RAW_INT_STAT for a detailed description of ACTIVITY bit. 0x0: RAW_ACTIVITY interrupt is inactive 0x1: RAW_ACTIVITY interrupt is active
bits : 8 - 8 (1 bit)
access : read-only

RAW_STOP_DET : See RAW_INT_STAT for a detailed description of STOP_DET bit. 0x0: RAW_STOP_DET interrupt is inactive 0x1: RAW_STOP_DET interrupt is active
bits : 9 - 9 (1 bit)
access : read-only

RAW_START_DET : See RAW_INT_STAT for a detailed description of START_DET bit. 0x0: RAW_START_DET interrupt is inactive 0x1: RAW_START_DET interrupt is active
bits : 10 - 10 (1 bit)
access : read-only

RAW_GEN_CALL : See RAW_INT_STAT for a detailed description of GEN_CALL bit. 0x0: RAW_GEN_CALL interrupt is inactive 0x1: RAW_GEN_CALL interrupt is active
bits : 11 - 11 (1 bit)
access : read-only

RAW_RESTART_DET : See RAW_INT_STAT for a detailed description of RESTART_DET bit. 0x0: RAW_RESTART_DET interrupt is inactive 0x1: RAW_RESTART_DET interrupt is active
bits : 12 - 12 (1 bit)
access : read-only

RAW_M_HOLD : See RAW_INT_STAT for a detailed description of M_HOLD bit. 0x0: RAW_M_HOLD interrupt is inactive 0x1: RAW_M_HOLD interrupt is active
bits : 13 - 13 (1 bit)
access : read-only

MASK_RX_UNDER : This bit masks the RAW_RX_UNDER interrupt in INT_STAT register. 0x0: RX_UNDER interrupt is masked 0x1: RX_UNDER interrupt is unmasked
bits : 0 - 0 (1 bit)
access : read-write

MASK_RX_OVER : This bit masks the RAW_RX_OVER interrupt in INT_STAT register. 0x0: RX_OVER interrupt is masked 0x1: RX_OVER interrupt is unmasked
bits : 1 - 1 (1 bit)
access : read-write

MASK_RX_FULL : This bit masks the RAW_RX_FULL interrupt in INT_STAT register. 0x0: RX_FULL interrupt is masked 0x1: RX_FULL interrupt is unmasked
bits : 2 - 2 (1 bit)
access : read-write

MASK_TX_OVER : This bit masks the RAW_TX_OVER interrupt in INT_STAT register. 0x0: TX_OVER interrupt is masked 0x1: TX_OVER interrupt is unmasked
bits : 3 - 3 (1 bit)
access : read-write

MASK_TX_EMPTY : This bit masks the RAW_TX_EMPTY interrupt in INT_STAT register. 0x0: TX_EMPTY interrupt is masked 0x1: TX_EMPTY interrupt is unmasked
bits : 4 - 4 (1 bit)
access : read-write

MASK_RD_REQ : This bit masks the RAW_RD_REQ interrupt in INT_STAT register. 0x0: RD_REQ interrupt is masked 0x1: RD_REQ interrupt is unmasked
bits : 5 - 5 (1 bit)
access : read-write

MASK_TX_ABORT : This bit masks the RAW_TX_ABORT interrupt in INT_STAT register. 0x0: TX_ABORT interrupt is masked 0x1: TX_ABORT interrupt is unmasked
bits : 6 - 6 (1 bit)
access : read-write

MASK_RX_DONE : This bit masks the RAW_RX_DONE interrupt in INT_STAT register. 0x0: RX_DONE interrupt is masked 0x1: RX_DONE interrupt is unmasked
bits : 7 - 7 (1 bit)
access : read-write

MASK_ACTIVITY : This bit masks the RAW_ACTIVITY interrupt in INT_STAT register. 0x0: ACTIVITY interrupt is masked 0x1: ACTIVITY interrupt is unmasked
bits : 8 - 8 (1 bit)
access : read-write

MASK_STOP_DET : This bit masks the RAW_STOP_DET interrupt in INT_STAT register. 0x0: STOP_DET interrupt is masked 0x1: STOP_DET interrupt is unmasked
bits : 9 - 9 (1 bit)
access : read-write

MASK_START_DET : This bit masks the RAW_START_DET interrupt in INT_STAT register. 0x0: START_DET interrupt is masked 0x1: START_DET interrupt is unmasked
bits : 10 - 10 (1 bit)
access : read-write

MASK_GEN_CALL : This bit masks the RAW_GEN_CALL interrupt in INT_STAT register. 0x0: GEN_CALL interrupt is masked 0x1: GEN_CALL interrupt is unmasked
bits : 11 - 11 (1 bit)
access : read-write

RX_UNDER : Set if the processor attempts to read the receive buffer when it is empty by reading from the DATA_CMD register. If the module is disabled (EN[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when en goes to 0, this interrupt is cleared. 0x0: RX_UNDER interrupt is inactive 0x1: RX_UNDER interrupt is active
bits : 0 - 0 (1 bit)
access : read-only

RX_OVER : Set if the receive buffer is completely filled to 8 and an additional byte is received from an external I2C device. The I2C acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (EN[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when en goes to 0, this interrupt is cleared. 0x0: RX_OVER interrupt is inactive 0x1: RX_OVER interrupt is active
bits : 1 - 1 (1 bit)
access : read-only

RX_FULL : Set when the receive buffer reaches or goes above the FIFO_THD threshold in the RX_FIFO_THD register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (EN[0]=0), the RX FIFO is flushed and held in reset therefore the RX FIFO is not full. So this bit is cleared once the ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. 0x0: RX_FULL interrupt is inactive 0x1: RX_FULL interrupt is active
bits : 2 - 2 (1 bit)
access : read-only

TX_OVER : Set during transmit if the transmit buffer is filled to 8 and the processor attempts to issue another I2C command by writing to the DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when en goes to 0, this interrupt is cleared. Value: 0x0: TX_OVER interrupt is inactive 0x1: TX_OVER interrupt is active
bits : 3 - 3 (1 bit)
access : read-only

TX_EMPTY : The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the CTRL register. When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the TX_TL register. When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the TX_FIFO_THD register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When EN[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with en=0, this bit is set to 0. Value: 0x0: TX_EMPTY interrupt is inactive 0x1: TX_EMPTY interrupt is active
bits : 4 - 4 (1 bit)
access : read-only

RD_REQ : This bit is set to 1 when I2C is acting as a slave and another I2C master is attempting to read data from I2C. The I2C holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the DATA_CMD register. This bit is set to 0 just after the processor reads the CLR_RD_REQ register. Value: 0x0: RD_REQ interrupt is inactive 0x1: RD_REQ interrupt is active
bits : 5 - 5 (1 bit)
access : read-only

TX_ABORT : This bit indicates if I2C, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the TX_ABORT_SRC register indicates the reason why the transmit abort takes places. Note: The I2C flushes/resets/empties only the TX_FIFO whenever there is a transmit abort caused by any of the events tracked by the TX_ABORT_SRC register. The TX FIFO remains in this flushed state until the register CLR_TX_ABORT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface. 0x0: TX_ABORT interrupt is inactive 0x1: TX_ABORT interrupt is active
bits : 6 - 6 (1 bit)
access : read-only

RX_DONE : When the I2C is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. 0x0: RX_DONE interrupt is inactive 0x1: RX_DONE interrupt is active
bits : 7 - 7 (1 bit)
access : read-only

ACTIVITY : This bit captures I2C activity and stays set until it is cleared. There are four ways to clear it. Disabling the I2C Reading the CLR_ACTIVITY register Reading the CLR_INT register System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the I2C module is idle, this bit remains set until cleared, indicating that there was activity on the bus. 0x0: RAW_INT_ACTIVITY interrupt is inactive 0x1: RAW_INT_ACTIVITY interrupt is active
bits : 8 - 8 (1 bit)
access : read-only

STOP_DET : Indicates whether a STOP condition has occurred on the I2C interface regardless of whether I2C is operating in slave or master mode. In Slave Mode: If CTRL[7] = 0x1 (STOP_DET_INT), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_INT = 0x1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (S_ADDR). If CTRL[7] = 0x0 (STOP_DET_INT), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: If CTRL[10] = 0x1 (STOP_DET_M_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. If CTRL[10] = 0x0 (STOP_DET_M_ACTIVE),the STOP_DET interrupt will be issued irrespective of whether master is active or not. 0x0: STOP_DET interrupt is inactive 0x1: STOP_DET interrupt is active
bits : 9 - 9 (1 bit)
access : read-only

START_DET : Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether I2C is operating in slave or master mode. 0x0: START_DET interrupt is inactive 0x1: START_DET interrupt is active
bits : 10 - 10 (1 bit)
access : read-only

GEN_CALL : Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling I2C or when the CPU reads bit 0 of the CLR_GEN_CALL register. I2C stores the received data in the RX buffer. 0x0: GEN_CALL interrupt is inactive 0x1: GEN_CALL interrupt is active
bits : 11 - 11 (1 bit)
access : read-only

RESTART_DET : Indicates whether a RESTART condition has occurred on the I2C interface when I2C is operating in Slave mode and the slave is being addressed. Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore I2C does not generate the RESTART_DET interrupt. 0x0: RESTART_DET interrupt is inactive 0x1: RESTART_DET interrupt is active
bits : 12 - 12 (1 bit)
access : read-only

M_HOLD : Indicates whether master is holding the bus and TX FIFO is empty. 0x0: MASTER_ON_HOLD interrupt is inactive 0x1: MASTER_ON_HOLD interrupt is active
bits : 13 - 13 (1 bit)
access : read-only

THD : Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in RAW_INT_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.
bits : 0 - 7 (8 bit)
access : read-write

THD : Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in RAW_INT_STAT register). The valid range is 0 ~ 255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries.
bits : 0 - 7 (8 bit)
access : read-write

TARGET : This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the TARGET and S_ADDR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself it can transmit to only a slave
bits : 0 - 9 (10 bit)
access : read-write

TX_CTRL : If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the I2C. 0x0: GENERAL_CALL byte transmission 0x1: START byte transmission
bits : 10 - 10 (1 bit)
access : read-write

SPECIAL : This bit indicates whether software performs a Device-ID or General Call or START BYTE command. 0x0: Disables programming of GENERAL_CALL or START_BYTE transmission 0x1: Enables programming of GENERAL_CALL or START_BYTE transmission
bits : 11 - 11 (1 bit)
access : read-write

CLR_INT : Read this register to clear the combined interrupt, all individual interrupts, and the TX_ABORT_SRC register. This bit does not clear hardware clearable interrupts but software clearable interrupts.
bits : 0 - 0 (1 bit)
access : read-only

CLR_RX_UNDER : Read this register to clear the RX_UNDER interrupt (bit 0) of the RAW_INT_STAT register
bits : 0 - 0 (1 bit)
access : read-only

CLR_RX_OVER : Read this register to clear the RX_OVER interrupt (bit 1) of the RAW_INT_STAT register
bits : 0 - 0 (1 bit)
access : read-only

CLR_TX_OVER : Read this register to clear the TX_OVER interrupt (bit 2) of the RAW_INT_STAT register
bits : 0 - 0 (1 bit)
access : read-only

CLR_RD_REQ : Read this register to clear the RD_REQ interrupt (bit 5) of the RAW_INT_STAT register.
bits : 0 - 0 (1 bit)
access : read-only

CLR_TX_ABORT : Read this register to clear the TX_ABORT interrupt (bit 6) of the RAW_INT_STAT register, and the TX_ABORT_SRC register.
bits : 0 - 0 (1 bit)
access : read-only

CLR_RX_DONE : Read this register to clear the RX_DONE interrupt (bit 7) of the RAW_INT_STAT register.
bits : 0 - 0 (1 bit)
access : read-only

CLR_ACTIVITY : Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the RAW_INT_STAT register.
bits : 0 - 0 (1 bit)
access : read-only

CLR_STOP_DET : Read this register to clear the STOP_DET interrupt (bit 9) of the RAW_INT_STAT register.
bits : 0 - 0 (1 bit)
access : read-only

CLR_START_DET : Read this register to clear the START_DET interrupt (bit 10) of the RAW_INT_STAT register.
bits : 0 - 0 (1 bit)
access : read-only

CLR_GEN_CALL : Read this register to clear the GEN_CALL interrupt (bit 11) of RAW_INT_STAT register.
bits : 0 - 0 (1 bit)
access : read-only

ACTIVITY : Controls whether the I2C is enabled. Software can disable I2C while it is active. However, it is important that care be taken to ensure that I2C is disabled properly. A recommended procedure is described in Disabling I2C . When I2C is disabled, the following occurs: The TX FIFO and RX FIFO get flushed. Status bits in the INTR_STAT register are still active until I2C goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the I2C stops the current transfer at the end of the current byte and does not acknowledge the transfer. 0x0: I2C is disabled 0x1: I2C is enabled
bits : 0 - 0 (1 bit)
access : read-only

ABORT : When set, the controller initiates the transfer abort. The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the TX FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. 0x0: ABORT operation not in progress 0x1: ABORT operation in progress
bits : 1 - 1 (1 bit)
access : read-write

TX_CMD_BLOCK : In Master mode 0x0: TX Command execution not blocked 0x1: TX Command execution blocked
bits : 2 - 2 (1 bit)
access : read-write

ACTIVITY : I2C Activity Status. 0x0: I2C is idle 0x1: I2C is active
bits : 0 - 0 (1 bit)
access : read-only

TX_FIFO_NF : Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0x0: TX FIFO is full 0x1: TX FIFO not full
bits : 1 - 1 (1 bit)
access : read-only

TX_FIFO_CE : Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0x0: TX FIFO not empty 0x1: TX FIFO is empty
bits : 2 - 2 (1 bit)
access : read-only

RX_FIFO_NE : Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries it is cleared when the receive FIFO is empty. 0x0: RX FIFO is empty 0x1: RX FIFO not empty
bits : 3 - 3 (1 bit)
access : read-only

RX_FIFO_CF : Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0x0: RX FIFO not full 0x1: RX FIFO is full
bits : 4 - 4 (1 bit)
access : read-only

M_ACTIVITY : Master Activity Status. When the Master is not in the IDLE state, this bit is set. Note: STAS[0], ACTIVITY bit,-is the OR of S_ACTIVITY and M_ACTIVITY bits. 0x0: Master is idle 0x1: Master not idle
bits : 5 - 5 (1 bit)
access : read-only

S_ACTIVITY : Slave Activity Status. When the Slaveis not in the IDLE state, this bit is set. 0x0: Slave is idle 0x1: Slave not idle
bits : 6 - 6 (1 bit)
access : read-only

LEVEL : Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.
bits : 0 - 3 (4 bit)
access : read-only

LEVEL : Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.
bits : 0 - 3 (4 bit)
access : read-only

TX_HOLD : Sets the required SDA hold time in units of clock period, when I2C acts as a transmitter.
bits : 0 - 15 (16 bit)
access : read-write

RX_HOLD : Sets the required SDA hold time in units of clock period, when I2C acts as a receiver.
bits : 16 - 23 (8 bit)
access : read-write

S_ADDR : The S_ADDR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only S_ADDR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. Note:The default values cannot be any of the reserved address locations: 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the S_ADDR or TARGET to a reserved value. Refer to Table 10 7 I2C Definition of bits in first byte for a complete list of these reserved values.
bits : 0 - 9 (10 bit)
access : read-write

ABORT_7B_NOACK : his field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Role of I2C: Master-Transmitter or Master-Receiver 0x0: This abort is not generated 0x1: This abort is generated because of NACK for 7-bit address
bits : 0 - 0 (1 bit)
access : read-only

ABORT_10B1_NOACK : This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Role of I2C: Master-Transmitter or Master-Receiver 0x0: This abort is not generated 0x1: Byte 1 of 10Bit Address not ACKed by any slave
bits : 1 - 1 (1 bit)
access : read-only

ABORT_10B2_NOACK : This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Role of I2C: Master-Transmitter or Master-Receiver 0x0: This abort is not generated 0x1: Byte 2 of 10Bit Address not ACKed by any slave
bits : 2 - 2 (1 bit)
access : read-only

ABORT_TX_NOACK : This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Role of I2C:Master-Transmitter 0x0: Transmitted data non-ACKed by addressed slave-scenario not present 0x1 : Transmitted data not ACKed by addressed slave
bits : 3 - 3 (1 bit)
access : read-only

ABORT_GCALL_NOACK : This field indicates that I2C in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Role of I2C: Master-Transmitter 0x0: GCALL not ACKed by any slave-scenario not present 0x1: GCALL not ACKed by any slave
bits : 4 - 4 (1 bit)
access : read-only

ABORT_GCALL_RD : This field indicates that I2C in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (DATA_CMD[9] is set to 1). Role of I2C: Master-Transmitter 0x0: GCALL is followed by read from bus-scenario not present 0x1: GCALL is followed by read from bus
bits : 5 - 5 (1 bit)
access : read-only

ABORT_HS_ACKDET : This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Role of I2C: Master 0x0: HS Master code ACKed in HS Mode- scenario not present 0x1: HS Master code ACKed in HS Mode
bits : 6 - 6 (1 bit)
access : read-only

ABORT_SBYTE_ACKDET : This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Role of I2C: Master 0x0: ACK detected for START byte- scenario not present 0x1: ACK detected for START byte
bits : 7 - 7 (1 bit)
access : read-only

ABORT_HS_NORSTRT : This field indicates that the restart is disabled (RESTART_EN bit (CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. Role of I2C: Master-Transmitter or Master-Receiver 0x0: User trying to switch Master to HS mode when RESTART disabled- scenario not present 0x1: User trying to switch Master to HS mode when RESTART disabled
bits : 8 - 8 (1 bit)
access : read-only

ABORT_SBYTE_NORSTRT : To clear Bit 9, the source of the ABORT_SBYTE_NORSTRT must be fixed first restart must be enabled (CTRL[5]=1), the SPECIAL bit must be cleared (TARGET[11]), or the GC_OR_START bit must be cleared TARGET[10]). Once the source of the ABORT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABORT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (RESTART_EN bit (CTRL[5]) =0) and the user is trying to send a START Byte. Role of I2C: Master 0x0: User trying to send START byte when RESTART disabled- scenario not present 0x1: User trying to send START byte when RESTART disabled
bits : 9 - 9 (1 bit)
access : read-only

ABORT_10B_RD_NORSTR : This field indicates that the restart is disabled (RESTART_EN bit (CON[5]) =0) and the master sends a read command in 10-bit addressing mode. Role of I2C: Master-Receiver Value: 0x0: Master not trying to read in 10Bit addressing mode when RESTART disabled 0x1: Master trying to read in 10Bit addressing mode when RESTART disabled
bits : 10 - 10 (1 bit)
access : read-only

ABORT_MASTER_DIS : This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Role of I2C: Master-Transmitter or Master-Receiver 0x: User initiating master operation when MASTER disabled- scenario not present 0x1: User intitating master operation when MASTER disabled
bits : 11 - 11 (1 bit)
access : read-only

ABORT_LOST : This field specifies that the Master has lost arbitration, or if TX_ABORT_SRC[14] is also set, then the slave transmitter has lost arbitration. Role of I2C: Master-Transmitter or Slave-Transmitter 0x0: Master or Slave-Transmitter lost arbitration- scenario not present 0x1: Master or Slave-Transmitter lost arbitration
bits : 12 - 12 (1 bit)
access : read-only

ABORT_SLVFLUSH_TXFIFO : This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABORT interrupt to flush old data in TX FIFO. Role of I2C: Slave-Transmitter 0x0: Slave flushes existing data in TX-FIFO upon getting read command- scenario not present 0x1: Slave flushes existing data in TX-FIFO upon getting read command
bits : 13 - 13 (1 bit)
access : read-only

ABORT_S_ARBLOST : This field indicates that a Slave has lost the bus while transmitting data to a remote master. TX_ABORT_SRC[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then I2C no longer own the bus. Role of I2C: Slave-Transmitter 0x0: Slave lost arbitration to remote master- scenario not present 0x1 : Slave lost arbitration to remote master
bits : 14 - 14 (1 bit)
access : read-only

ABORT_SLVRD_INTX : When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of DATA_CMD register. Role of I2C: Slave-Transmitter 0x0: Slave trying to transmit to remote master in read mode- scenario not present 0x1: Slave trying to transmit to remote master in read mode
bits : 15 - 15 (1 bit)
access : read-only

ABORT_USER_ABORT : This is a master-mode-only bit. Master has detected the transfer abort (EN[1]) Role of I2C: Master-Transmitter 0x0: Transfer abort detected by master- scenario not present 0x1: Transfer abort detected by master
bits : 16 - 16 (1 bit)
access : read-only

TX_FLUSH_CNT : This field indicates the number of TX FIFO Data Commands which are flushed due to TX_ABORT interrupt. It is cleared whenever I2C is disabled. Role of I2C: Master-Transmitter or Slave-Transmitter
bits : 23 - 31 (9 bit)
access : read-only

RX_EN : Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. 0x0: Receive FIFO DMA channel disabled 0x1: Receive FIFO DMA channel enabled
bits : 0 - 0 (1 bit)
access : read-write

TX_EN : Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. 0x0: Transmit FIFO DMA channel disabled 0x1: Transmit FIFO DMA channel enabled
bits : 1 - 1 (1 bit)
access : read-write

LEVEL : Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic.
bits : 0 - 2 (3 bit)
access : read-write

LEVEL : Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic.
bits : 0 - 2 (3 bit)
access : read-write

SETUP : SDA Setup. It is recommended that if the required delay is 1000ns, then for a clk frequency of 10 MHz, SDA_SETUP should be programmed to a value of 11. SDA_SETUP must be programmed with a minimum value of 2
bits : 0 - 7 (8 bit)
access : read-write

ACK_GEN_CALL : ACK General Call. When set to 1, I2C responds with an ACK (by asserting data_oe) when it receives a General Call. Otherwise, I2C responds with a NACK (by negating data_oe). 0x0: Generate NACK for General Call 0x1: Generate ACK for a General Call
bits : 0 - 0 (1 bit)
access : read-write

EN : EN Status. This bit always reflects the value driven on the output port en. When read as 1, I2C is deemed to be in an enabled state. When read as 0, I2C is deemed completely inactive. Note:The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read S_RX_DATA_LOST (bit 2) and S_DIS_BUSY (bit 1). 0x0: I2C disabled 0x1: I2C enabled
bits : 0 - 0 (1 bit)
access : read-only

S_DIS_BUSY : Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the ENregister from 1 to 0. This bit is set when the CPU writes a 0 to the EN register while • I2C is receiving the address byte of the Slave-Transmitter operation from a remote master or • Address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, I2C is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in I2C (S_ADDR register) OR if the transfer is completed before ENABLE is set to 0 but has not taken effect. Note: If the remote I2C master terminates the transfer with a STOP condition before the I2C has a chance to NACK a transfer, and EN[0] has been set to 0, then this bit will also be set to 1. When read as 0, I2C is deemed to have been disabled when there is master activity, or when the I2C bus is idle. Note: The CPU can safely read this bit when EN (bit 0) is read as 0. 0x0: Slave is disabled when it is idle 0x1: Slave is disabled when it is active
bits : 1 - 1 (1 bit)
access : read-only

S_RX_DATA_LOST : Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of EN from 1 to 0. When read as 1, I2C is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. Note: If the remote I2C master terminates the transfer with a STOP condition before the I2C has a chance to NACK a transfer, and EN[0] has been set to 0, then this bit is also set to 1. When read as 0, I2C is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. Note: The CPU can safely read this bit when EN (bit 0) is read as 0. 0x0: Slave RX Data is not lost 0x1: Slave RX Data is lost
bits : 2 - 2 (1 bit)
access : read-only

FS_SPKLEN : This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in clock cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1 hardware prevents values less than this being written, and if attempted results in 1 being set.
bits : 0 - 7 (8 bit)
access : read-write

HS_SPKLEN : This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in clock cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic for more information, refer to Spike Suppression This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1 hardware prevents values less than this being written, and if attempted results in 1 being set.
bits : 0 - 7 (8 bit)
access : read-write

HS_ADDR : This bit field holds the value of the I2C High Speed mode master code. High Speed mode master codes are reserved 8-bit codes (00001xxx) that are not used for slave addressing or other purposes. Each master has its unique master code up to eight high-speed mode masters can be present on the same I2C bus system. Valid values are from 0 to 7. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect.
bits : 0 - 2 (3 bit)
access : read-write