EN

SCLK_CFG

RX_FIFO_RST

TX_FIFO_RST

RX_DMA

RST_RX_DMA

TX_DMA

RST_TX_DMA

LEFT_RX_BUF

LEFT_TX_HDG

RIGHT_RX_BUF

RIGHT_TX_HDG

CLK_CFG

RX_CH_EN

TX_CH_EN

RX_CFG

TX_CFG

INT_STAT

INT_MASK

RX_EN

RX_OVER

TX_OVER

RX_FIFO_CFG

TX_FIFO_CFG

RX_FIFO_FLUSH

TX_FIFO_FLUSH

TX_EN

CLK_EN

I2S_EN : I2S enable. This bit enables or disables I2S. A disable on this bit overrides any other block or channel enables and flushes all FIFOs. Value: 0x0: I2S disabled. 0x1: I2S enabled
bits : 0 - 0 (1 bit)
access : read-write

SCLK_GAT : These bits are used to program the gating of sclk. The programmed gating value must be less than or equal to the largest configured/programmed audio resolution to prevent the truncating of RX/TX data. The I2S Clock Generation block must be disabled (CLK_EN[0] = 0) before making any changes in this value. • 0x0 (NO_CLOCK_GATING): Clock gating is disabled • 0x1 (CLOCK_CYCLES_12): Gating after 12 sclk cycles • 0x2 (CLOCK_CYCLES_16): Gating after 16 sclk cycles • 0x3 (CLOCK_CYCLES_20): Gating after 20 sclk cycles • 0x4 (CLOCK_CYCLES_24): Gating after 24 sclk cycles Exists: This register is only relevant when component is configured to be a master (I2S_MODE_EN = 1).
bits : 0 - 2 (3 bit)
access : read-write

WS_SCLK : These bits are used to program the number of sclk cycles for which the word select line (ws_out) stays in the left or right sample mode. The I2S Clock Generation block must be disabled (CLK_EN[0] = 0) prior to any changes in this value. • 0x0: 16 sclk cycles • 0x1: 24 sclk cycles • 0x2: 32 sclk cycles Exists: This register is only relevant when component is configured to be a master (I2S_MODE_EN = 1).
bits : 3 - 4 (2 bit)
access : read-write

RX_FIFO_RST : Receiver FIFO Reset. Writing a 1 to this register flushes all the RX FIFOs (this is a self clearing bit). The Receiver Block must be disabled before writing to this bit. • 0x0: Does not flush the RX FIFO • 0x1: Flushes the RX FIFO
bits : 0 - 0 (1 bit)
access : write-only

TX_FIFO_RST : Transmitter FIFO Reset. Writing a 1 to this register flushes all the TX FIFOs (this is a self clearing bit). The Transmitter Block must be disabled prior to writing this bit. Value: • 0x0: Does not flush the TX FIFO • 0x1: Flushes the TX FIFO
bits : 0 - 0 (1 bit)
access : write-only

RX_DMA : Receiver Block DMA Register. These bits are used to cycle repeatedly through the enabled receive channel, reading stereo data pairs.
bits : 0 - 0 (1 bit)
access : read-write

RST_RX_DMA : Reset Receiver Block DMA Register. Writing a 1 to this self-clearing register resets the RXDMA register mid-cycle to point to the enabled Receive channel. • 0x0: No effect. • 0x1: Reset receiver block DMA register.
bits : 0 - 0 (1 bit)
access : write-only

TX_DMA : Transmitter Block DMA Register. These bits are used to cycle repeatedly through the enabled transmit channel to allow writing of stereo data pairs.
bits : 0 - 0 (1 bit)
access : read-write

RST_TX_DMA : Reset Transmitter Block DMA Register. Writing a 1 to this self-clearing register resets the TXDMA register mid-cycle to point to the enabled Transmit channel. • 0x0: No effect. • 0x1: Reset transmitter block DMA register.
bits : 0 - 0 (1 bit)
access : write-only

LEFT_RX_BUF : The left stereo data received serially from the receive channel input (sdi). If the RX FIFO is full and the two-stage read operation (for instance, a read from LEFT_RX_BUF register followed by a read from RIGHT_RX_BUF register) is not performed before the start of the next stereo pair, then the new data is lost and an overrun interrupt occurs. (data already in the RX FIFO is preserved.) Note: Before reading this register again, the right stereo data must be read from RRBRx or the status/interrupts will not be valid.
bits : 0 - 31 (32 bit)
access : read-only

LEFT_TX_HDG : The left stereo data to be transmitted serially through the transmit channel output (sdo) is written through this register. Writing is a two-stage process: 1. A write to this register passes the left stereo sample to the transmitter. 2. This MUST be followed by writing the right stereo sample to the RIGHT_TX_HDG register. Data must only be written to the FIFO when it is not full. Any attempt to write to a full FIFO results in that data being lost and an overrun interrupt being generated.
bits : 0 - 31 (32 bit)
access : write-only

RIGHT_RX_BUF : The right stereo data received serially from the receive channel input (sdi) is read through this register. If the RX FIFO is full and the two-stage read operation (for instance, read from LEFT_RX_BUF register followed by a read from RIGHT_RX_BUF register) is not performed before the start of the next stereo pair, then the new data is lost and an overrun interrupt occurs. (Data already in the RX FIFO is preserved.) Note: Prior to reading this register, the left stereo data MUST be read from LEFT_RX_BUF register, or the status/interrupts will not be valid.
bits : 0 - 31 (32 bit)
access : read-only

RIGHT_TX_HDG : The right stereo data to be transmitted serially through the transmit channel output (sdo) is written through this register. Writing is a two-stage process: 1. A left stereo sample MUST be written to the LTHR register. 2. A write to this register passes the right stereo sample to the transmitter. Data should only be written to the FIFO when it is not full. Any attempt to write to a full FIFO results in that data being lost and an overrun interrupt being generated.
bits : 0 - 31 (32 bit)
access : write-only

DIV : ratio = 1/(div + 2). Duty cycle is not 50 when the number is odd. For example: div = 0, ratio = 1/2
bits : 0 - 11 (12 bit)
access : read-write

DIV_EN : enable i2s clock divider
bits : 16 - 16 (1 bit)
access : read-write

CLK_SRC_SEL : clock divider source select 0: 96M, 1: 32M
bits : 18 - 18 (1 bit)
access : read-write

RX_CH_EN : Receive channel enable. This bit enables/disables a receive channel. On enable, the channel begins receiving on the next left stereo cycle. A global disable of I2S (EN[0] = 0) or the Receiver block (RX_EN[0] = 0) overrides this value. • 0x0: Receive Channel Disable • 0x1: Receive Channel Enable
bits : 0 - 0 (1 bit)
access : read-write

TX_CH_EN : Transmit channel enable. This bit enables/disables a transmit channel. On enable, the channel begins transmitting on the next left stereo cycle. A global disable of I2S (EN[0] = 0) or Transmitter block (TX_EN[0] = 0) overrides this value. • 0x0: Transmit Channel Disable • 0x1: Transmit Channel Enable
bits : 0 - 0 (1 bit)
access : read-write

WORD_LEN : These bits are used to program the desired data resolution of the receiver and enables the LSB of the incoming left (or right) word to be placed in the LSB of the LEFT_RX_BUF (or RIGHT_RX_BUF) register. Programmed data resolution must be less than or equal to 0x5. If the selected resolution is greater than the 0x5, the receive channel defaults back to 0x5. The channel must be disabled prior to any changes in this value(RX_EN[0] = 0). • 0x0: Ignore the word length • 0x1: 12-bit data resolution of the receiver. • 0x2: 16-bit data resolution of the receiver. • 0x3: 20-bit data resolution of the receiver. • 0x4: 24-bit data resolution of the receiver. • 0x5: 32-bit data resolution of the receiver.
bits : 0 - 2 (3 bit)
access : read-write

WORD_LEN : These bits are used to program the data resolution of the transmitter and ensures the MSB of the data is transmitted first. Programmed resolution must be less than or equal to 0x5. If the selected resolution is greater than 0x5, the transmit channel defaults back to 0x5. The channel must be disabled prior to any changes in this value(TX_EN[0] = 0). • 0x0: Ignore the word length • 0x1: 12-bit data resolution of the transmitter. • 0x2: 16-bit data resolution of the transmitter. • 0x3: 20-bit data resolution of the transmitter. • 0x4: 24-bit data resolution of the transmitter. • 0x5: 32-bit data resolution of the transmitter.
bits : 0 - 2 (3 bit)
access : read-write

RX_DATA_AVL : Status of Receive Data Available interrupt. This bit denotes the status of the RX FIFO trigger level. • 0x1: RX FIFO trigger level is reached • 0x0: RX FIFO trigger level is not reached
bits : 0 - 0 (1 bit)
access : read-only

RX_FIFO_OVER : Status of Data Overrun interrupt for the RX channel. Incoming data lost due to a full RX FIFO. • 0x0: RX FIFO write valid • 0x1: RX FIFO write overrun
bits : 1 - 1 (1 bit)
access : read-only

TX_FIFO_EMPTY : Status of Transmit Empty Trigger interrupt. This bit specifies whether the TX FIFO trigger level has reached or not. TX FIFO is empty. • 0x0: TX FIFO trigger level is reached • 0x1: TX FIFO trigger level is not reached
bits : 4 - 4 (1 bit)
access : read-only

TX_FIFO_OVER : Status of Data Overrun interrupt for the TX channel. This bit specifies whether the TX FIFO write is valid or an overrun. Attempt to write to full TX FIFO. • 0x0: TX FIFO write valid • 0x1: TX FIFO write overrun
bits : 5 - 5 (1 bit)
access : read-only

RX_DAM : Mask RX FIFO Data Available interrupt. This bit masks or unmasks an RX FIFO Data Available interrupt. • 0x1: Disable RX FIFO data available interrupt • 0x0: Enable RX FIFO data available interrupt
bits : 0 - 0 (1 bit)
access : read-write

RX_FOM : Mask RX FIFO Overrun interrupt. This bit masks or unmasks an RX FIFO Overrun interrupt. • 0x1: Disable RX FIFO Overrun interrupt • 0x0: Enable RX FIFO Overrun interrupt
bits : 1 - 1 (1 bit)
access : read-write

TX_FEM : Mask TX FIFO Empty interrupt. This bit masks or unmasks a TX FIFO Empty interrupt. • 0x1: Disable TX FIFO Empty interrupt • 0x0: Enable TX FIFO Empty interrupt
bits : 4 - 4 (1 bit)
access : read-write

TX_FOM : Mask TX FIFO Overrun interrupt. This bit masks or unmasks a TX FIFO overrun interrupt. • 0x1: Disable TX FIFO Overrun interrupt • 0x0: Enable TX FIFO Overrun interrupt
bits : 5 - 5 (1 bit)
access : read-write

RX_EN : Receiver block enable. This bit enables or disables the receiver. A disable on this bit overrides any individual receive channel enables. Value: • 0x0: Receiver disabled • 0x1: Receiver enabled
bits : 0 - 0 (1 bit)
access : read-write

RX_CLR_FDO : Read this bit to clear the RX FIFO Data Overrun interrupt. • 0x0: RX FIFO write valid • 0x1: RX FIFO write overrun
bits : 0 - 0 (1 bit)
access : read-only

TX_CLR_FDO : Read this bit to clear the TX FIFO Data Overrun interrupt. • 0x0: TX FIFO write valid • 0x1: TX FIFO write overrun
bits : 0 - 0 (1 bit)
access : read-only

RX_FIFO_TL : These bits program the trigger level in the RX FIFO at which the Received Data Available interrupt is generated. Trigger Level = Programmed Value + 1 • 0x0: Interrupt trigger when FIFO level is 1. • 0x1: Interrupt trigger when FIFO level is 2. • 0x2: Interrupt trigger when FIFO level is 3. • 0x3: Interrupt trigger when FIFO level is 4. • 0x4: Interrupt trigger when FIFO level is 5. • 0x5: Interrupt trigger when FIFO level is 6. • 0x6: Interrupt trigger when FIFO level is 7. • 0x7: Interrupt trigger when FIFO level is 8. • 0x8: Interrupt trigger when FIFO level is 9. • 0x9: Interrupt trigger when FIFO level is 10. • 0xA: Interrupt trigger when FIFO level is 11. • 0xB: Interrupt trigger when FIFO level is 12. • 0xC: Interrupt trigger when FIFO level is 13. • 0xD: Interrupt trigger when FIFO level is 14. • 0xE: Interrupt trigger when FIFO level is 15. • 0xF: Interrupt trigger when FIFO level is 16.
bits : 0 - 3 (4 bit)
access : read-write

TX_FIFO_TL : These bits program the trigger level in the RX FIFO at which the Received Data Available interrupt is generated. Trigger Level = Programmed Value + 1 • 0x0: Interrupt trigger when FIFO level is 1. • 0x1: Interrupt trigger when FIFO level is 2. • 0x2: Interrupt trigger when FIFO level is 3. • 0x3: Interrupt trigger when FIFO level is 4. • 0x4: Interrupt trigger when FIFO level is 5. • 0x5: Interrupt trigger when FIFO level is 6. • 0x6: Interrupt trigger when FIFO level is 7. • 0x7: Interrupt trigger when FIFO level is 8. • 0x8: Interrupt trigger when FIFO level is 9. • 0x9: Interrupt trigger when FIFO level is 10. • 0xA: Interrupt trigger when FIFO level is 11. • 0xB: Interrupt trigger when FIFO level is 12. • 0xC: Interrupt trigger when FIFO level is 13. • 0xD: Interrupt trigger when FIFO level is 14. • 0xE: Interrupt trigger when FIFO level is 15. • 0xF: Interrupt trigger when FIFO level is 16.
bits : 0 - 3 (4 bit)
access : read-write

RX_FIFO_RST : Receive Channel FIFO Reset. Writing a 1 to this register flushes an individual RX FIFO (This is a self clearing bit.). A RX channel or block must be disabled prior to writing to this bit. • 0x0: Does not flush an individual RX FIFO. • 0x1: Flushes an individual RX FIFO.
bits : 0 - 0 (1 bit)
access : write-only

TX_FIFO_RST : Transmit Channel FIFO Reset. Writing a 1 to this register flushes an individual TX FIFO (This is a self clearing bit.). A TX channel or block must be disabled prior to writing to this bit. Value: • 0x0: Does not flush an individual TX FIFO. • 0x1: Flushes an individual TX FIFO.
bits : 0 - 0 (1 bit)
access : write-only

TX_EN : Transmitter block enable. This bit enables or disables the transmitter. A disable on this bit overrides any individual transmit channel enables. Value: • 0x0: Transmitter disabled • 0x1: Transmitter enabled
bits : 0 - 0 (1 bit)
access : read-write

CLK_EN : Clock Generation enable/disable. This bit enables or disables the clock generation signals when I2S is a master. • 0x0: Clock generation disabled • 0x1: Clock generation enabled Note: When the I2S is configured as a slave, this register serves no purpose.
bits : 0 - 0 (1 bit)
access : read-write