CTRL

TIMES_CFG

DATA_CFG

ADDR

START_ADDR

RX_END_ADDR

TX_END_ADDR

STAT

CLK_CFG

ACTION : 0x0: Do Nothing. 0x1: Switch off. 0x2: Stop the clock. 0x3: Switch on and receive ATR. Re-enable clock if clock is stoped. 0x4: Trigger warm reset and receive ATR. 0x5: Receive. 0x6: Transmit. 0x7: Transmit, followed by RX
bits : 0 - 2 (3 bit)
access : write-only

RX_RETYR_MC : Receive Retries Maximum Clear. This register clears ‘STAT.RX_RETRY_MAX’. 0x0: No effect 0x1: Clear
bits : 8 - 8 (1 bit)
access : write-only

TX_RETYR_MC : Transmit Retries Maximum Clear. This register clears ‘STAT.TX_RETRY_MAX’. 0x0: No effect 0x1: Clear
bits : 12 - 12 (1 bit)
access : write-only

IRQ_DONE_CLR : Interrupt source done clear. This register clears interrupt source ‘STAT.INT_DONE’. 0x0: No effect 0x1: Clear
bits : 20 - 20 (1 bit)
access : write-only

IRQ_RX_EC : Interrupt source rx_err clear. This register clears interrupt source ‘STAT.INT_RX_ERR’. 0x0: No effect 0x1: Clear
bits : 21 - 21 (1 bit)
access : write-only

IRQ_RETYR_EC : Interrupt source retry_err clear. This register clears interrupt source ‘STAT.IRQ_RETYR_ERR’. 0x0: No effect 0x1: Clear
bits : 22 - 22 (1 bit)
access : write-only

IRQ_DMA_EC : Interrupt source dma_err clear. This register clears interrupt source ‘STAT.INT_DMA_ERR’. 0x0: No effect 0x1: Clear
bits : 23 - 23 (1 bit)
access : write-only

IRQ_STAT_EC : Interrupt source state_err clear. This register clears interrupt source ‘STAT.INT_STAT_ERR’. 0x0: No effect 0x1: Clear
bits : 24 - 24 (1 bit)
access : write-only

IRQ_PRESENCE_CLR : Interrupt source presence clear. This register clears interrupt source ‘STAT.INT_PRESENCE’. 0x0: No effect 0x1: Clear
bits : 25 - 25 (1 bit)
access : write-only

IRQ_TEST_CLR : Interrupt Test Clear. This register clears test interrupt (has higher priority than ‘INT_TEST_SET’) 0x0: No effect 0x1: Clear
bits : 30 - 30 (1 bit)
access : write-only

IRQ_TEST_SET : Interrupt Test Set. This register sets test interrupt 0x0: No effect 0x1: Set
bits : 31 - 31 (1 bit)
access : write-only

GUARD_TIME : Guard time in [ETU]. Time between the leading edges of two consecutive characters.
bits : 0 - 9 (10 bit)
access : read-write

WAIT_TIME : • Wait time in [ETU]. • Maximum card response time (leading edge to leading edge).
bits : 12 - 29 (18 bit)
access : read-write

CODING : Coding Convention. 0x0: Default. High = 1, LSB first. 0x1: Inverse. High = 0, MSB first.
bits : 0 - 0 (1 bit)
access : read-write

DETECT_CODING : Detect Coding Convention. Automatically detect coding convention during ATR receiption. 0x0: Disable 0x1: Enable
bits : 1 - 1 (1 bit)
access : read-write

RETRY_LIMIT : • Retries Limit. • Maximum number of issued retries before giving up.
bits : 4 - 6 (3 bit)
access : read-write

ADDR_FRAC : Address Fraction. Byte selection.
bits : 0 - 1 (2 bit)
access : read-only

ADDR : • Address. • Current address relative to base_addr.
bits : 2 - 19 (18 bit)
access : read-only

START_ADDR : • Address. • Current address relative to base_addr.
bits : 2 - 19 (18 bit)
access : read-write

BASE_ADDR : Base Address. Base Address for RX and TX Buffer.
bits : 20 - 31 (12 bit)
access : read-write

RX_END_AF : RX End Address Fraction. Byte selection.
bits : 0 - 1 (2 bit)
access : read-only

RX_END_ADDR : • RX End Address. • End address of receive buffer, relative to base_addr.
bits : 2 - 19 (18 bit)
access : read-only

TX_END_AF : TX End Address Fraction. Byte selection.
bits : 0 - 1 (2 bit)
access : read-only

TX_END_ADDR : TX End Address. • End address of transmit buffer, relative to base_addr.
bits : 2 - 19 (18 bit)
access : read-only

PWR_STAT : Power States. 0x0: SIM is unpowered. 0x1: Power up SIM. RST asserted(low). Clock stopped. IO is tristate. 0x2: Power up SIM. RST asserted(low). Clock is running. IO is high. 0x3: Power up SIM. RST asserted(low). Clock is running. IO is tristate. 0x4: Power up SIM. RST asserted(low). Clock stopped. IO is low. 0x5: Preparing clock stop. 0x6: Clock stopped. 0x7: Exiting clock stop 0x8: SIM is idle, no communication is ongoing. 0x9: RX TS Character. 0xA: RX TS Character. 0XB: Receive. 0xC: Transmit. 0xD: Transmit and Receive
bits : 0 - 3 (4 bit)
access : read-only

IO_STAT : Receive Retries Maximum Clear. This register clears ‘STAT.RX_RETRY_MAX’. 0x0: No effect 0x1: Clear
bits : 4 - 6 (3 bit)
access : read-only

RX_RETRY_MAX : Receive Retries Maximum. Maximum number of seen receive retries after parity error.
bits : 8 - 10 (3 bit)
access : read-only

TX_RETRY_MAX : Transmit Retries Maximum. Maximum number of seen transmit retries after error signaling by SIM.
bits : 12 - 14 (3 bit)
access : read-only

BUSY : Status of SIM interface. 0x0: Idle 0x1: Busy
bits : 16 - 16 (1 bit)
access : read-only

PRESENCE_STAT : Status of presence IO. 0x0: Absent 0x1: Presence
bits : 17 - 17 (1 bit)
access : read-only

IRQ_DONE : Interrupt Done. Requeted operation has been completed. 0x0: No interrupt 0x1: Active
bits : 20 - 20 (1 bit)
access : read-only

IRQ_RX_ERR : Interrupt RX Error. No or incomplete or unexpected data. 0x0: No interrupt 0x1: Active
bits : 21 - 21 (1 bit)
access : read-only

IRQ_RETRY_ERR : Interrupt Retry Error. Maximum number of retries exceeded. 0x0: No interrupt 0x1: Active
bits : 22 - 22 (1 bit)
access : read-only

IRQ_DMA_ERR : Interrupt DMA Error. DMA read/write operation could not be issued. 0x0: No interrupt 0x1: Active
bits : 23 - 23 (1 bit)
access : read-only

IRQ_STAT_ERR : Interrupt State Error. Action rerquested while busy or unsupported transition. 0x0: No interrupt 0x1: Active
bits : 24 - 24 (1 bit)
access : read-only

IRQ_PRESENCE : Interrupt Presence. SIM card presence changed. Inserted or removed. 0x0: No interrupt 0x1: Active
bits : 25 - 25 (1 bit)
access : read-only

IRQ_TEST : Interrupt Test. Test interrupt for connection check. 0x0: No interrupt 0x1: Active
bits : 30 - 30 (1 bit)
access : read-only

ETU_DIV : Divide SIM clock by this value+1 to define ETU length. The reset value is the one, needed for the ATR.
bits : 0 - 9 (10 bit)
access : read-write

CLK_DIV : • Clock Division. • Divide system clock by this value + 1.
bits : 16 - 23 (8 bit)
access : read-write

CLK_STOP_SEL : Clock Stop Select. Value of the clock output during stopped clock. 0x0: Low 0x1: High
bits : 31 - 31 (1 bit)
access : read-write