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PIN_MUX

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection :

Registers

MSIO_PAD_CFG1

DPAD_IN_EN

DPAD_PULL_TYPE

DPAD_OUT_EN

MSIO_VAL

DPAD_MUX_CTRL_00_07

DPAD_MUX_CTRL_08_15

DPAD_MUX_CTRL_16_23

DPAD_MUX_CTRL_24_31

AON_PAD_MUX_CTRL

MSIO_PAD_MUX_CTRL

ANO_PAD_CTRL0

ANO_PAD_CTRL1

MSIO_PAD_CFG0


MSIO_PAD_CFG1

MISO PAD Configuration 1 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSIO_PAD_CFG1 MSIO_PAD_CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSIO_A_EN MSIO_R_TYPE DEP_CTRL_RD DEP_CTRL_WR MSIO_MCU_OVE SADC_CLK_SEL SADC_CLK_EN

MSIO_A_EN : Analog enable control for MSIO Pad 0x0: Analog mode 0x1: Digital mode
bits : 0 - 4 (5 bit)
access : read-write

MSIO_R_TYPE : MSIO resistor type 0x0: Pull down 0x1: Pull up
bits : 8 - 12 (5 bit)
access : read-write

DEP_CTRL_RD : deep sleep control comm timer register read bit
bits : 15 - 15 (1 bit)
access : read-only

DEP_CTRL_WR : deep sleep control comm timer register write bit
bits : 16 - 21 (6 bit)
access : read-write

MSIO_MCU_OVE : Use the setting from MCU domain, Only valid when MCU domain is ON 0x0: Disable MSIOx digital setting 0x1: Enable MSIOx digital setting
bits : 22 - 26 (5 bit)
access : read-write

SADC_CLK_SEL : ADC clock select 0x0: 16 M 0x1: 8 M 0x2: 4 M 0x3: 2 M 0x4, 0x6: 1.6 M 0x5, 0x7: 1 M
bits : 28 - 30 (3 bit)
access : read-write

SADC_CLK_EN : ADC clock Enable 0x0: Disable ADC clock 0x1: Enable ADC clock
bits : 31 - 31 (1 bit)
access : read-write


DPAD_IN_EN

Resistor enable active lO inputs to the RETENTION PAD
address_offset : 0x1CD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPAD_IN_EN DPAD_IN_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DPAD_IN_EN

DPAD_IN_EN : Resistor enable active lO inputs to the RETENTION PAD 0x0: Enable resistor inputs to pad (GPIO_0 – GPIO_31) 0x1: Disable resistor inputs to pad (GPIO_ 0 – GPIO_31)
bits : 0 - 31 (32 bit)
access : read-write


DPAD_PULL_TYPE

Resistor type inputs to the RETENTION PAD.
address_offset : 0x1CE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPAD_PULL_TYPE DPAD_PULL_TYPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DPAD_R_TYPE

DPAD_R_TYPE : Resistor type inputs to the RETENTION PAD. 0x0: Pull down (when DPAD_IN_EN = 0) 0x1: Pull up (when DPAD_IN_EN = 0)
bits : 0 - 31 (32 bit)
access : read-write


DPAD_OUT_EN

Output enable active lO inputs to the RETENTION PAD
address_offset : 0x1CE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPAD_OUT_EN DPAD_OUT_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DPAD_OUT_EN

DPAD_OUT_EN : Output enable active lO inputs to the RETENTION PAD 0x0: Enable output. 0x1: Disable output.
bits : 0 - 31 (32 bit)
access : read-write


MSIO_VAL

MSIO Digital value register
address_offset : 0x1CF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSIO_VAL MSIO_VAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSIO_VAL

MSIO_VAL : MSIO Digital value (when MSIO_PAD_CFG1.MSIO_A_EN = 1)
bits : 0 - 4 (5 bit)
access : read-write


DPAD_MUX_CTRL_00_07

DPAD mux control GPIO_0 – GPIO_7 register
address_offset : 0x1D10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPAD_MUX_CTRL_00_07 DPAD_MUX_CTRL_00_07 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DPAD_MUX_SEL_00 DPAD_MUX_SEL_01 DPAD_MUX_SEL_02 DPAD_MUX_SEL_03 DPAD_MUX_SEL_04 DPAD_MUX_SEL_05 DPAD_MUX_SEL_06 DPAD_MUX_SEL_07

DPAD_MUX_SEL_00 : Mode for DPAD 0
bits : 0 - 3 (4 bit)
access : read-write

DPAD_MUX_SEL_01 : Mode for DPAD 1
bits : 4 - 7 (4 bit)
access : read-write

DPAD_MUX_SEL_02 : Mode for DPAD 2
bits : 8 - 11 (4 bit)
access : read-write

DPAD_MUX_SEL_03 : Mode for DPAD 3
bits : 12 - 15 (4 bit)
access : read-write

DPAD_MUX_SEL_04 : Mode for DPAD 4
bits : 16 - 19 (4 bit)
access : read-write

DPAD_MUX_SEL_05 : Mode for DPAD 5
bits : 20 - 23 (4 bit)
access : read-write

DPAD_MUX_SEL_06 : Mode for DPAD 6
bits : 24 - 27 (4 bit)
access : read-write

DPAD_MUX_SEL_07 : Mode for DPAD 7
bits : 28 - 31 (4 bit)
access : read-write


DPAD_MUX_CTRL_08_15

DPAD mux control GPIO_8 – GPIO_15 register
address_offset : 0x1D14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPAD_MUX_CTRL_08_15 DPAD_MUX_CTRL_08_15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DPAD_MUX_SEL_08 DPAD_MUX_SEL_09 DPAD_MUX_SEL_10 DPAD_MUX_SEL_11 DPAD_MUX_SEL_12 DPAD_MUX_SEL_13 DPAD_MUX_SEL_14 DPAD_MUX_SEL_15

DPAD_MUX_SEL_08 : Mode for DPAD 8
bits : 0 - 3 (4 bit)
access : read-write

DPAD_MUX_SEL_09 : Mode for DPAD 9
bits : 4 - 7 (4 bit)
access : read-write

DPAD_MUX_SEL_10 : Mode for DPAD 10
bits : 8 - 11 (4 bit)
access : read-write

DPAD_MUX_SEL_11 : Mode for DPAD 11
bits : 12 - 15 (4 bit)
access : read-write

DPAD_MUX_SEL_12 : Mode for DPAD 12
bits : 16 - 19 (4 bit)
access : read-write

DPAD_MUX_SEL_13 : Mode for DPAD 13
bits : 20 - 23 (4 bit)
access : read-write

DPAD_MUX_SEL_14 : Mode for DPAD 14
bits : 24 - 27 (4 bit)
access : read-write

DPAD_MUX_SEL_15 : Mode for DPAD 15
bits : 28 - 31 (4 bit)
access : read-write


DPAD_MUX_CTRL_16_23

DPAD mux control GPIO_16 – GPIO_23 register
address_offset : 0x1D18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPAD_MUX_CTRL_16_23 DPAD_MUX_CTRL_16_23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DPAD_MUX_SEL_16 DPAD_MUX_SEL_17 DPAD_MUX_SEL_18 DPAD_MUX_SEL_19 DPAD_MUX_SEL_20 DPAD_MUX_SEL_21 DPAD_MUX_SELL_22 DPAD_MUX_SEL_23

DPAD_MUX_SEL_16 : Mode for DPAD 16
bits : 0 - 3 (4 bit)
access : read-write

DPAD_MUX_SEL_17 : Mode for DPAD 17
bits : 4 - 7 (4 bit)
access : read-write

DPAD_MUX_SEL_18 : Mode for DPAD 18
bits : 8 - 11 (4 bit)
access : read-write

DPAD_MUX_SEL_19 : Mode for DPAD 19
bits : 12 - 15 (4 bit)
access : read-write

DPAD_MUX_SEL_20 : Mode for DPAD 20
bits : 16 - 19 (4 bit)
access : read-write

DPAD_MUX_SEL_21 : Mode for DPAD 21
bits : 20 - 23 (4 bit)
access : read-write

DPAD_MUX_SELL_22 : Mode for DPAD 22
bits : 24 - 27 (4 bit)
access : read-write

DPAD_MUX_SEL_23 : Mode for DPAD 23
bits : 28 - 31 (4 bit)
access : read-write


DPAD_MUX_CTRL_24_31

DPAD mux control GPIO_24– GPIO_31 register
address_offset : 0x1D1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPAD_MUX_CTRL_24_31 DPAD_MUX_CTRL_24_31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DPAD_MUX_SEL_24 DPAD_MUX_SEL_25 DPAD_MUX_SEL_26 DPAD_MUX_SEL_27 DPAD_MUX_SEL_28 DPAD_MUX_SEL_29 DPAD_MUX_SEL_30 DPAD_MUX_SEL_31

DPAD_MUX_SEL_24 : Mode for DPAD 24
bits : 0 - 3 (4 bit)
access : read-write

DPAD_MUX_SEL_25 : Mode for DPAD 25
bits : 4 - 7 (4 bit)
access : read-write

DPAD_MUX_SEL_26 : Mode for DPAD 26
bits : 8 - 11 (4 bit)
access : read-write

DPAD_MUX_SEL_27 : Mode for DPAD 27
bits : 12 - 15 (4 bit)
access : read-write

DPAD_MUX_SEL_28 : Mode for DPAD 28
bits : 16 - 19 (4 bit)
access : read-write

DPAD_MUX_SEL_29 : Mode for DPAD 29
bits : 20 - 23 (4 bit)
access : read-write

DPAD_MUX_SEL_30 : Mode for DPAD 30
bits : 24 - 27 (4 bit)
access : read-write

DPAD_MUX_SEL_31 : Mode for DPAD 31
bits : 28 - 31 (4 bit)
access : read-write


AON_PAD_MUX_CTRL

Always-on PAD mux control register
address_offset : 0x1D60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AON_PAD_MUX_CTRL AON_PAD_MUX_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AON_PAD_MUX_SEL_01 AON_PAD_MUX_SEL_02 AON_PAD_MUX_SEL_03 AON_PAD_MUX_SEL_04 AON_PAD_MUX_SEL_05

AON_PAD_MUX_SEL_01 : Mode for AON PAD [1]
bits : 4 - 6 (3 bit)
access : read-write

AON_PAD_MUX_SEL_02 : Mode for AON PAD [2]
bits : 8 - 10 (3 bit)
access : read-write

AON_PAD_MUX_SEL_03 : Mode for AON PAD [3]
bits : 12 - 14 (3 bit)
access : read-write

AON_PAD_MUX_SEL_04 : Mode for AON PAD [4]
bits : 16 - 18 (3 bit)
access : read-write

AON_PAD_MUX_SEL_05 : Mode for AON PAD [5]
bits : 20 - 22 (3 bit)
access : read-write


MSIO_PAD_MUX_CTRL

Always-on PAD mux control register
address_offset : 0x1D64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSIO_PAD_MUX_CTRL MSIO_PAD_MUX_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSIO_PAD_MUX_SEL_00 MSIO_PAD_MUX_SELL_01 MSIO_PAD_MUX_SEL_02 MSIO_PAD_MUX_SEL_03 MSIO_PAD_MUX_SEL_04

MSIO_PAD_MUX_SEL_00 : Mode for MSIO PAD [0]
bits : 0 - 2 (3 bit)
access : read-write

MSIO_PAD_MUX_SELL_01 : Mode for MSIO PAD [1]
bits : 4 - 6 (3 bit)
access : read-write

MSIO_PAD_MUX_SEL_02 : Mode for MSIO PAD [2]
bits : 8 - 10 (3 bit)
access : read-write

MSIO_PAD_MUX_SEL_03 : Mode for MSIO PAD [3]
bits : 12 - 14 (3 bit)
access : read-write

MSIO_PAD_MUX_SEL_04 : Mode for MSIO PAD [4]
bits : 16 - 18 (3 bit)
access : read-write


ANO_PAD_CTRL0

AON PAD control 0 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANO_PAD_CTRL0 ANO_PAD_CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AON_R_EN AON_R_TYPE AON_MCU_OVE TIMER_CLK_SEL

AON_R_EN : Always on PAD resister enable 0x0: Enable AONx resistor 0x1: Disable AONx resistor
bits : 0 - 7 (8 bit)
access : read-write

AON_R_TYPE : Always on PAD resistor type 0x0: Pull down 0x1: Pull up
bits : 8 - 15 (8 bit)
access : read-write

AON_MCU_OVE : Use the setting from MCU domain, Only valid when MCU domain is ON 0x0: Disable AONx digital setting 0x1: Enable AONx digital setting
bits : 16 - 23 (8 bit)
access : read-write

TIMER_CLK_SEL : comm timer clock select 0x0: rng_osc_clk 0x1: rtc_osc_clk 0x2, 0x3: rng_2_osc_clk (an rng clock with better ppm)
bits : 28 - 29 (2 bit)
access : read-write


ANO_PAD_CTRL1

AON PAD control 0 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANO_PAD_CTRL1 ANO_PAD_CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AON_OUT_EN AON_OUT_VAL OVR_EN TIMER_RD_SEL

AON_OUT_EN : Always on PAD output enable (active low) 0x0: Enable AONx output 0x1: Disable AONx output
bits : 0 - 7 (8 bit)
access : read-write

AON_OUT_VAL : AON PAD output value (valid when oe_n = 0) 0x0: Drive AONx low 0x1: Drive AONx high
bits : 8 - 15 (8 bit)
access : read-write

OVR_EN : Enable override for all stdby_n and vdd_iso_n value
bits : 25 - 25 (1 bit)
access : read-write

TIMER_RD_SEL : Select which timer value to read 0x0: calendar timer 0x1: always on watchdog timer 0x2: sleep timer 0x3: Calendar timer alarm value
bits : 30 - 31 (2 bit)
access : read-write


MSIO_PAD_CFG0

MISO PAD Configuration 0 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSIO_PAD_CFG0 MSIO_PAD_CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSIO_R_EN MSIO_OUT MSIO_IN_EN MSIO_OUT_EN

MSIO_R_EN : MSIO resistor enable (active low) 0x0: Enable MSIOx resistor 0x1: Disable MSIOx resistor
bits : 0 - 4 (5 bit)
access : read-write

MSIO_OUT : MSIO Drive value (valid in output mode) 0x0: Drive MSIOx low 0x1: Drive MSIOx high
bits : 8 - 12 (5 bit)
access : read-write

MSIO_IN_EN : MSIO input enable (active low) 0x0: Enable MSIOx input 0x1: Disable MSIOx input
bits : 16 - 20 (5 bit)
access : read-write

MSIO_OUT_EN : MSIO output enable (active low) 0x0: Enable MSIOx output 0x1: Disable MSIOx output
bits : 24 - 28 (5 bit)
access : read-write



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