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PWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection :

Registers

MODE

COMPA1

COMPB0

COMPB1

COMPC0

COMPC1

AQ_CTRL

BREATH_PRD

HOLD

UPDATE

PRD

COMPA0


MODE

Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PAUSE BREATH_EN PD_A_EN PD_B_EN PD_C_EN

EN : Enable PWM. 0x0: Disable 0x1: Enable
bits : 0 - 0 (1 bit)
access : read-write

PAUSE : PWM pause signal. 0x0: Ongoing 0x1: Pause
bits : 1 - 1 (1 bit)
access : read-write

BREATH_EN : Breath mode enable. 0x0: flicker mode 0x1: breath mode
bits : 2 - 2 (1 bit)
access : read-write

PD_A_EN : PWM_A positive-drive mode enable. 0x0: negative-drive mode 0x1: positive-drive mode
bits : 3 - 3 (1 bit)
access : read-write

PD_B_EN : PWM_B positive-drive mode enable. 0x0: negative-drive mode 0x1: positive-drive mode
bits : 4 - 4 (1 bit)
access : read-write

PD_C_EN : PWM_C positive-drive mode enable. 0x0: negative-drive mode 0x1: positive-drive mode
bits : 5 - 5 (1 bit)
access : read-write


COMPA1

Compare A1 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPA1 COMPA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPA1

COMPA1 : PWM_A duty control register1
bits : 0 - 31 (32 bit)
access : read-write


COMPB0

Compare B0 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPB0 COMPB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPB0

COMPB0 : PWM_B duty control register0
bits : 0 - 31 (32 bit)
access : read-write


COMPB1

Compare B1 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPB1 COMPB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP_B1

COMP_B1 : PWM_B duty control register1
bits : 0 - 31 (32 bit)
access : read-write


COMPC0

Compare C0 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPC0 COMPC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPC0

COMPC0 : PWM_C duty control register0
bits : 0 - 31 (32 bit)
access : read-write


COMPC1

Compare C1 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPC1 COMPC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPC1

COMPC1 : PWM_C duty control register1
bits : 0 - 31 (32 bit)
access : read-write


AQ_CTRL

Action Qualifler Control Regiser
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AQ_CTRL AQ_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AQ_CTRL_A0 AQ_CTRL_A1 AQ_CTRL_B0 AQ_CTRL_B1 AQ_CTRL_C0 AQ_CTRL_C1

AQ_CTRL_A0 : Action of event CNT_CMPA0 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle
bits : 0 - 1 (2 bit)
access : read-write

AQ_CTRL_A1 : Action of event CNT_CMPA1 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle
bits : 2 - 3 (2 bit)
access : read-write

AQ_CTRL_B0 : Action of event CNT_CMPB0 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle
bits : 4 - 5 (2 bit)
access : read-write

AQ_CTRL_B1 : Action of event CNT_CMPB1 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle
bits : 6 - 7 (2 bit)
access : read-write

AQ_CTRL_C0 : Action of event CNT_CMPC0 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle
bits : 8 - 9 (2 bit)
access : read-write

AQ_CTRL_C1 : Action of event CNT_CMPC1 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle
bits : 10 - 11 (2 bit)
access : read-write


BREATH_PRD

Breath Period Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREATH_PRD BREATH_PRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BREATH_PRD

BREATH_PRD : Breath period register, i.e. the required time (number of clock) that the duty changes from 0% to 100% in breath mode.
bits : 0 - 31 (32 bit)
access : read-write


HOLD

Compare B1 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOLD HOLD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HOLD

HOLD : Breath hold control register. The value should be the required number of clock in breath hold state.
bits : 0 - 23 (24 bit)
access : read-write


UPDATE

Update Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPDATE UPDATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPDATE_SYNC_AG UPDATE_SYNC_AE UPDATE_SYNC_SPRD UPDATE_SYNC_SCMPA0 UPDATE_SYNC_SCMPA1 UPDATE_SYNC_SCMPB0 UPDATE_SYNC_SCMPB1 UPDATE_SYNC_SCMPC0 UPDATE_SYNC_SCMPC1 UPDATE_SYNC_SPAUSE UPDATE_SYNC_SBRPRD UPDATE_SYNC_SHOLD UPDATE_SYNC_SAQCTRL

UPDATE_SYNC_AG : All synchronous update ongoing 0x0: Not ongoing 0x1: Ongoing
bits : 0 - 0 (1 bit)
access : read-only

UPDATE_SYNC_AE : All synchronous update enable 0x0: Disable 0x1: Enable
bits : 1 - 1 (1 bit)
access : read-write

UPDATE_SYNC_SPRD : synchronous separate update enable of PRD(period) 0x0: Disable 0x1: Enable
bits : 8 - 8 (1 bit)
access : read-write

UPDATE_SYNC_SCMPA0 : synchronous separate update enable of CMPA0 0x0: Disable 0x1: Enable
bits : 9 - 9 (1 bit)
access : read-write

UPDATE_SYNC_SCMPA1 : synchronous separate update enable of CMPA1 0x0: Disable 0x1: Enable
bits : 10 - 10 (1 bit)
access : read-write

UPDATE_SYNC_SCMPB0 : synchronous separate update enable of CMPB0 0x0: Disable 0x1: Enable
bits : 11 - 11 (1 bit)
access : read-write

UPDATE_SYNC_SCMPB1 : synchronous separate update enable of CMPB1 0x0: Disable 0x1: Enable
bits : 12 - 12 (1 bit)
access : read-write

UPDATE_SYNC_SCMPC0 : synchronous separate update enable of CMPC0 0x0: Disable 0x1: Enable
bits : 13 - 13 (1 bit)
access : read-write

UPDATE_SYNC_SCMPC1 : synchronous separate update enable of CMPC1 0x0: Disable 0x1: Enable
bits : 14 - 14 (1 bit)
access : read-write

UPDATE_SYNC_SPAUSE : synchronous separate update enable of PAUSE 0x0: Disable 0x1: Enable
bits : 15 - 15 (1 bit)
access : read-write

UPDATE_SYNC_SBRPRD : synchronous separate update enable of BRPRD(breath period) 0x0: Disable 0x1: Enable
bits : 16 - 16 (1 bit)
access : read-write

UPDATE_SYNC_SHOLD : synchronous separate update enable of HOLD(hold period) 0x0: Disable 0x1: Enable
bits : 17 - 17 (1 bit)
access : read-write

UPDATE_SYNC_SAQCTRL : synchronous separate update enable of AQCTRL(action qualifler control) 0x0: Disable 0x1: Enable
bits : 18 - 18 (1 bit)
access : read-write


PRD

Period Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRD PRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRD

PRD : The period of PWM output, PRD=fCLK/fPWM
bits : 0 - 31 (32 bit)
access : read-write


COMPA0

Compare A0 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPA0 COMPA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPA0

COMPA0 : PWM_A duty control register0
bits : 0 - 31 (32 bit)
access : read-write



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