CTRL0

S_EN

BAUD

TX_FIFO_TL

RX_FIFO_TL

TX_FIFO_LEVEL

RX_FIFO_LEVEL

STAT

INT_MASK

INT_STAT

RAW_INT_STAT

TX_FIFO_OIC

RX_FIFO_OIC

CTRL1

RX_FIFO_UIC

MULTI_M_IC

INT_CLR

DMA_CTRL

DMA_TX_DL

DMA_RX_DL

DATA

SSI_EN

MW_CTRL

RX_SMP_DLY

SPI_CTRL

FRAME_FORMAT : Frame Format. Selects which serial protocol transfers the data. 0x0 (MOTOROLA_SPI): Motorolla SPI Frame Format 0x1 (TEXAS_SSP): Texas Instruments SSP Frame Format 0x2 (NS_MICROWIRE): National Microwire Frame Format 0x3 (RESERVED): Reserved value
bits : 4 - 5 (2 bit)
access : read-write

SERIAL_CLK_PHASE : Serial Clock Phase. Valid when the frame format (FRAME_FORMAT) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SERIAL_CLK_PHASE = 0, data are captured on the first edge of the serial clock. When SERIAL_CLK_PHASE = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data are captured on the second edge of the serial clock. 0x0 (SERIAL_CLK_PHASE_MIDDLE): Serial clock toggles in middle of first data bit 0x1 (SERIAL_CLK_PHASE_START): Serial clock toggles at start of first data bit
bits : 6 - 6 (1 bit)
access : read-write

SERIAL_CLK_POL : Serial Clock Polarity. Valid when the frame format (FRAME_FORMAT) is set to Motorola SPI. Used to select the polarity of the inactive serial clock, which is held inactive when the SPI master is not actively transferring data on the serial bus. 0x0 (SCLK_LOW): Inactive state of serial clock is low 0x1 (SCLK_HIGH): Inactive state of serial clock is high
bits : 7 - 7 (1 bit)
access : read-write

XFE_MODE : Transfer Mode. This transfer mode is only valid when the SPI is configured as master device. 0x0 - Transmit and Receive 0x1 - Transmit Only 0x2 - Receive Only 0x3 - EEPROM Read When SPI_FRF is not set to 2'b00. There are only two valid combinations: 0x1 - Write 0x2 - Read 0x0 (TX_AND_RX): Transmit and receive 0x1 (TX_ONLY): Transmit only mode or Write (SPI_FRAME_FORMAT != 0x0) 0x2 (RX_ONLY): Receive only mode or Read (SPI_FRAME_FORMAT!= 0x0) 0x3 (EEPROM_READ): EEPROM Read mode
bits : 8 - 9 (2 bit)
access : read-write

SHIFT_REG_LOOP : Shift Register Loop. Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input. 0x0 (NORMAL_MODE): Normal mode operation 0x1 (TESTING_MODE): Test mode: TX and RX shift reg connected
bits : 11 - 11 (1 bit)
access : read-write

CTRL_FRAME_SIZE : Control Frame Size. Selects the length of the control word for the Microwire frame format. 0x0 (SIZE_01_BIT): 1-bit Control Word 0x1 (SIZE_02_BIT): 2-bit Control Word 0x2 (SIZE_03_BIT): 3-bit Control Word 0x3 (SIZE_04_BIT): 4-bit Control Word 0x4 (SIZE_05_BIT): 5-bit Control Word 0x5 (SIZE_06_BIT): 6-bit Control Word 0x6 (SIZE_07_BIT): 7-bit Control Word 0x7 (SIZE_08_BIT): 8-bit Control Word 0x8 (SIZE_09_BIT): 9-bit Control Word 0x9 (SIZE_10_BIT): 10-bit Control Word 0xa (SIZE_11_BIT): 11-bit Control Word 0xb (SIZE_12_BIT): 12-bit Control Word 0xc (SIZE_13_BIT): 13-bit Control Word 0xd (SIZE_14_BIT): 14-bit Control Word 0xe (SIZE_15_BIT): 15-bit Control Word 0xf (SIZE_16_BIT): 16-bit Control Word
bits : 12 - 15 (4 bit)
access : read-write

DATA_FRAME_SIZE : Data Frame Size in 32-bit transfer size mode. Used to select the data frame size in 32-bit transfer mode. When the data frame size is programmed to be less than 32 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You are responsible for making sure that transmit data is right-justified before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data. Note: When SPI_FRAME_FORMAT is not set to 0x0. - DFS value should be multiple of 2 if SPI_FRAME_FORMAT = 0x01, - DFS value should be multiple of 4 if SPI_FRAME_FORMAT = 0x10. 0x3 (FRAME_04BITS): 4-bit serial data transfer 0x4 (FRAME_05BITS): 5-bit serial data transfer 0x5 (FRAME_06BITS): 6-bit serial data transfer 0x6 (FRAME_07BITS): 7-bit serial data transfer 0x7 (FRAME_08BITS): 8-bit serial data transfer 0x8 (FRAME_09BITS): 9-bit serial data transfer 0x9 (FRAME_10BITS): 10-bit serial data transfer 0xa (FRAME_11BITS): 11-bit serial data transfer 0xb (FRAME_12BITS): 12-bit serial data transfer 0xc (FRAME_13BITS): 13-bit serial data transfer 0xd (FRAME_14BITS): 14-bit serial data transfer 0xe (FRAME_15BITS): 15-bit serial data transfer 0xf (FRAME_16BITS): 16-bit serial data transfer 0x10 (FRAME_17BITS): 17-bit serial data transfer 0x11 (FRAME_18BITS): 18-bit serial data transfer 0x12 (FRAME_19BITS): 19-bit serial data transfer 0x13 (FRAME_20BITS): 20-bit serial data transfer 0x14 (FRAME_21BITS): 21-bit serial data transfer 0x15 (FRAME_22BITS): 22-bit serial data transfer 0x16 (FRAME_23BITS): 23-bit serial data transfer 0x17 (FRAME_24BITS): 24-bit serial data transfer 0x18 (FRAME_25BITS): 25-bit serial data transfer 0x19 (FRAME_26BITS): 26-bit serial data transfer 0x1a (FRAME_27BITS): 27-bit serial data transfer 0x1b (FRAME_28BITS): 28-bit serial data transfer 0x1c (FRAME_29BITS): 29-bit serial data transfer 0x1d (FRAME_30BITS): 30-bit serial data transfer 0x1e (FRAME_31BITS): 31-bit serial data transfer 0x1f (FRAME_32BITS): 32-bit serial data transfer
bits : 16 - 20 (5 bit)
access : read-write

SPI_FRAME_FORMAT : SPI Frame Format: Selects data frame format for Transmitting/Receiving the data Bits. 0x0 (STD_SPI_FRAME_FORMAT): Standard SPI Frame Format 0x1 (DUAL_SPI_FRAME_FORMAT): Dual SPI Frame Format 0x2 (QUAD_SPI_FRAME_FORMAT): Quad SPI Frame Format 0x3: Reserved
bits : 21 - 22 (2 bit)
access : read-write

S_ST_EN : Slave Select Toggle Enable. When operating in SPI mode with clock phase (SERIAL_CLK_PHASE) set to 0, this register controls the behavior of the slave select line (CS) between data frames. If this register field is set to 1 the CS line will toggle between consecutive data frames, with the serial clock (sclk) being held to its default value while CS is high if this register field is set to 0 the CS will stay low and sclk will run continuously for the duration of the transfer. Note: When the SPI is configured as a slave, this register serves no purpose.
bits : 24 - 24 (1 bit)
access : read-write

S_SEL_EN : Slave Select Enable. Each bit in this register corresponds to a slave select line (CSn) from the SPI master. 0x0 (NOT_SELECTED): No slave selected 0x1 (SELECTED): Slave is selected Note: When the SPI is configured as a slave, this register serves no purpose.
bits : 0 - 1 (2 bit)
access : read-write

SSI_CLK_DIV : SSI Clock Divider. The LSB for this field is always set to 0 and is unaffected by a write operation, which ensures an even value is held in this register. If the value is 0, the serial output clock (sclk_out) is disabled. The frequency of the sclk_out is derived from the following equation: Fsclk_out = Fssi_clk/SSI_CLK_DIV Note: When the SPI is configured as a slave, this register serves no purpose.
bits : 0 - 15 (16 bit)
access : read-write

TX_FIFO_THD : Transmit FIFO Threshold. Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256 this register is sized to the number of address bits needed to access the FIFO. If you attempt to set this value greater than or equal to the depth of the FIFO, this field is not written and retains its current value.When the number of transmit FIFO entries is less than or equal to this value, the transmit FIFO empty interrupt is triggered.
bits : 0 - 2 (3 bit)
access : read-write

RX_FIFO_THD : Receive FIFO Threshold. Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256. This register is sized to the number of address bits needed to access the FIFO. If you attempt to set this value greater than the depth of the FIFO, this field is not written and retains its current value. When the number of receive FIFO entries is greater than or equal to this value + 1, the receive FIFO full interrupt is triggered.
bits : 0 - 2 (3 bit)
access : read-write

TX_FIFO_LEVEL : Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.
bits : 0 - 3 (4 bit)
access : read-only

RX_FIFO_LEVEL : Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.
bits : 0 - 3 (4 bit)
access : read-only

SSI_BUSY : SSI Busy Flag. When set, indicates that a serial transfer is in progress when cleared indicates that the SPI is idle or disabled. 0x0 (INACTIVE): SPI is idle or disabled 0x1 (ACTIVE): SPI is actively transferring data
bits : 0 - 0 (1 bit)
access : read-only

TX_FIFO_NF : Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0x0 (FULL): Transmit FIFO is full 0x1 (NOT_FULL): Transmit FIFO is not Full
bits : 1 - 1 (1 bit)
access : read-only

TX_FIFO_EMPTY : Transmit FIFO Empty. When the transmit FIFO is completely empty, this bit is set. When the transmit FIFO contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0x0 (NOT_EMPTY): Transmit FIFO is not empty 0x1 (EMPTY): Transmit FIFO is empty
bits : 2 - 2 (1 bit)
access : read-only

RX_FIFO_NE : Receive FIFO Not Empty. Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO. 0x0 (EMPTY): Receive FIFO is empty 0x1 (NOT_EMPTY): Receive FIFO is not empty
bits : 3 - 3 (1 bit)
access : read-only

RX_FIFO_FULL : Receive FIFO Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0x0 (NOT_FULL): Receive FIFO is not full 0x1 (FULL): Receive FIFO is full
bits : 4 - 4 (1 bit)
access : read-only

TX_ERR : Transmission Error. Set if the transmit FIFO is empty when a transfer is started. Data from the previous transmission is resent on the txd line. This bit is cleared when read. 0x0 (NO_ERROR): No Error 0x1 (TX_ERROR): Transmission Error Note: When the SPI is configured as a master, this register serves no purpose.
bits : 5 - 5 (1 bit)
access : read-only

DATA_COLN_ERR : Data Collision Error. This bit will be set if MISO input is asserted by other master, when the SPI master is in the middle of the transfer. This informs the processor that the last data transfer was halted before completion. This bit is cleared when read.
bits : 6 - 6 (1 bit)
access : read-only

TX_FIFO_EIS : Transmit FIFO Empty Interrupt Mask 0x0 (MASKED): Disable txe_intr interrupt 0x1 (UNMASKED): Enable txe_intr interrupt
bits : 0 - 0 (1 bit)
access : read-write

TX_FIFO_OIS : Transmit FIFO Overflow Interrupt Mask 0x0 (MASKED): Disable txo_intr interrupt 0x1 (UNMASKED): Enable txo_intr interrupt
bits : 1 - 1 (1 bit)
access : read-write

RX_FIFO_UIS : Receive FIFO Underflow Interrupt Mask 0x0 (MASKED): Disable rxu_intr interrupt 0x1 (UNMASKED): Enable rxu_intr interrupt
bits : 2 - 2 (1 bit)
access : read-write

RX_FIFO_OIS : Receive FIFO Overflow Interrupt Mask 0x0 (MASKED): Disable rxo_intr interrupt 0x1 (UNMASKED): Enable rxo_intr interrupt
bits : 3 - 3 (1 bit)
access : read-write

RX_FIFO_FIS : Receive FIFO Full Interrupt Mask 0x0 (MASKED): Disable rxf_intr interrupt 0x1 (UNMASKED): Enable rxf_intr interrupt
bits : 4 - 4 (1 bit)
access : read-write

MULTI_M_CIM : Multi-Master Contention Interrupt Mask. 0x0 (MASKED): Disable mst_intr interrupt 0x1 (UNMASKED): Enable mst_intr interrupt
bits : 5 - 5 (1 bit)
access : read-write

TX_FIFO_EIS : Transmit FIFO Empty Interrupt Status 0x0 (INACTIVE): txe_intr interrupt is not active after be enabled 0x1 (ACTIVE): txe_intr interrupt is active after be enabled
bits : 0 - 0 (1 bit)
access : read-only

TX_FIFO_OIS : Transmit FIFO Overflow Interrupt Status 0x0 (INACTIVE): txo_intr interrupt is not active after be enabled 0x1 (ACTIVE): txo_intr interrupt is active after be enabled
bits : 1 - 1 (1 bit)
access : read-only

RX_FIFO_UIS : Receive FIFO Underflow Interrupt Status 0x0 (INACTIVE): rxu_intr interrupt is not active after be enabled 0x1 (ACTIVE): rxu_intr interrupt is active after be enabled
bits : 2 - 2 (1 bit)
access : read-only

RX_FIFO_OIS : Receive FIFO Overflow Interrupt Status 0x0 (INACTIVE): rxo_intr interrupt is not active after be enabled 0x1 (ACTIVE): rxo_intr interrupt is active after be enabled
bits : 3 - 3 (1 bit)
access : read-only

RX_FIFO_FIS : Receive FIFO Full Interrupt Status 0x0 (INACTIVE): rxf_intr interrupt is not active after be enabled 0x1 (ACTIVE): rxf_intr interrupt is full after be enabled
bits : 4 - 4 (1 bit)
access : read-only

MULTI_M_CIS : Multi-Master Contention Interrupt Status 0x0 (INACTIVE): mst_intr interrupt is not active after be enabled 0x1 (ACTIVE): mst_intr interrupt is full after be enabled
bits : 5 - 5 (1 bit)
access : read-only

TX_FIFO_ERIS : Transmit FIFO Empty Raw Interrupt Status 0x0 (INACTIVE): txe_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): txe_intr interrupt is active prior be enabled
bits : 0 - 0 (1 bit)
access : read-only

TX_FIFO_ORIS : Transmit FIFO Overflow Raw Interrupt Status 0x0 (INACTIVE): txo_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): txo_intr interrupt is active prior be enabled
bits : 1 - 1 (1 bit)
access : read-only

RX_FIFO_URIS : Receive FIFO Underflow Raw Interrupt Status 0x0 (INACTIVE): rxu_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): rxu_intr interrupt is active prior to be enabled
bits : 2 - 2 (1 bit)
access : read-only

RX_FIFO_ORIS : Receive FIFO Overflow Raw Interrupt Status 0x1 (ACTIVE): rxo_intr interrupt is not active prior to be enabled 0x0 (INACTIVE): rxo_intr interrupt is active prior be enabled
bits : 3 - 3 (1 bit)
access : read-only

RX_FIFO_FRIS : Receive FIFO Full Raw Interrupt Status 0x0 (INACTIVE): rxf_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): rxf_intr interrupt is active prior to be enabled
bits : 4 - 4 (1 bit)
access : read-only

MULTI_M_CRIS : Multi-Master Contention Raw Interrupt Status 0x0 (INACTIVE): mst_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): mst_intr interrupt is full prior to be enabled
bits : 5 - 5 (1 bit)
access : read-only

TX_FIFO_OIC : Clear Transmit FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the txo_intr interrupt writing has no effect.
bits : 0 - 0 (1 bit)
access : read-only

RX_FIFO_OIC : Clear Receive FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the rxo_intr interrupt writing has no effect.
bits : 0 - 0 (1 bit)
access : read-only

NUM_DATA_FRAME : Number of Data Frames. When XFE_MODE = 0x2 or XFE_MODE = 0x3, this register field sets the number of data frames to be continuously received by the SPI. The SPI continues to receive serial data until the number of data frames received is equal to thisregister value plus 1, which enables you to receive up to 64KB of data in a continuous transfer. Note: When the SPI is configured as a slave, this register serves no purpose.
bits : 0 - 15 (16 bit)
access : read-write

RX_FIFO_UIC : Clear Receive FIFO Underflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the rxu_intr interrupt writing has no effect.
bits : 0 - 0 (1 bit)
access : read-only

MULTI_M_IC : Clear Multi-Master Contention Interrupt. This register reflects the status of the interrupt. A read from this register clears the mst_intr interrupt writing has no effect.
bits : 0 - 0 (1 bit)
access : read-only

INT_CLR : Clear Interrupts. This register is set if any of the interrupts below are active. A read clears the txo_intr, rxu_intr, rxo_intr, and the mst_intr interrupts. Writing to this register has no effect.
bits : 0 - 0 (1 bit)
access : read-only

RX_DMA_EN : Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel 0x0 (DISABLE): Receive DMA disabled 0x1 (ENABLED): Receive DMA enabled
bits : 0 - 0 (1 bit)
access : read-write

TX_DMA_EN : Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. 0x0 (DISABLE): Transmit DMA disabled 0x1 (ENABLED): Transmit DMA enabled
bits : 1 - 1 (1 bit)
access : read-write

DMA_TX_DL : Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TX_DMA_EN = 1.
bits : 0 - 2 (3 bit)
access : read-write

DMA_RX_DL : Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level =DMA_RX_DL+1 that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or above this field value + 1, and RX_DMA_EN=1.
bits : 0 - 2 (3 bit)
access : read-write

DATA : Data Register. When writing to this register, you must right-justify the data. Read data are automatically right-justified.
bits : 0 - 31 (32 bit)
access : read-write

SSI_EN : SSI Enable. Enables and disables all SPI operations. When disabled, all serial transfers are halted immediately. Transmit and receive FIFO buffers are cleared when the device is disabled. 0x0 (DISABLE): Disables Serial Transfer 0x1 (ENABLED): Enables Serial Transfer
bits : 0 - 0 (1 bit)
access : read-write

MW_XFE_MODE : Microwire Transfer Mode. Defines whether the Microwire transfer is sequential or non-sequential. When sequential mode is used, only one control word is needed to transmit or receive a block of data words. When non-sequential mode is used, there must be a control word for each data word that is transmitted or received. 0x0 (NON_SEQUENTIAL): Non-Sequential Microwire Transfer 0x1 (SEQUENTIAL): Sequential Microwire Transfer
bits : 0 - 0 (1 bit)
access : read-write

MW_DIR_DW : Microwire Control. Defines the direction of the data word when the Microwire serial protocol is used. 0x0 (RECEIVE): SPI receives data 0x1 (TRANSMIT): SPI transmits data
bits : 1 - 1 (1 bit)
access : read-write

MW_HSG : Microwire Handshaking. Used to enable and disable the busy/ready handshaking interface for the Microwire protocol. When enabled, the SPI checks for a ready status from the target slave, after the transfer of the last data/control bit, before clearing the SSI_BUSY status in the DATA register. 0x0 (DISABLE): Handshaking interface is disabled 0x1 (ENABLED): Handshaking interface is enabled Note: When the SPI is configured as a slave, this register serves no purpose.
bits : 2 - 2 (1 bit)
access : read-write

RX_SMP_DLY : RX Sample Delay. This register is used to delay the sample of the rxd input port. Each value represents a single ssi_clk delay on the sample of rxd. The maximum value is 7. Note: When the SPI is configured as a slave, this register serves no purpose.
bits : 0 - 7 (8 bit)
access : read-write

XFE_FORMAT_AI : Address and instruction transfer format. Selects whether QSPI will transmit instruction/address either in Standard SPI mode or the SPI mode selected in CTRL0.SPI_FRAME_FORMATfield. Value: 0x0 - Instruction and Address will be sent in Standard SPI Mode. 0x1 - Instruction will be sent in Standard SPI Mode and Address will be sent in the mode specified by CTRL0.SPI_FRAME_FORMAT. 0x2 - Both Instruction and Address will be sent in the mode specified by SPI_FRAME_FORMAT. 0x3 - Reserved.
bits : 0 - 1 (2 bit)
access : read-write

ADDR_LEN : Address Length. This bit defines Length of Address to be transmitted. Only after this much bits are programmed in to the FIFO the transfer can begin. 0x0 (ADDR_LEN_0): 0-bit Address Width 0x1 (ADDR_LEN_1): 4-bit Address Width 0x2 (ADDR_LEN_2): 8-bit Address Width 0x3 (ADDR_LEN_3): 12-bit Address Width 0x4 (ADDR_LEN_4): 16-bit Address Width 0x5 (ADDR_LEN_5): 20-bit Address Width 0x6 (ADDR_LEN_6): 24-bit Address Width 0x7 (ADDR_LEN_7): 28-bit Address Width 0x8 (ADDR_LEN_8): 32-bit Address Width 0x9 (ADDR_LEN_9): 36-bit Address Width 0xa (ADDR_LEN_10): 40-bit Address Width 0xb (ADDR_LEN_11): 44-bit Address Width 0xc (ADDR_LEN_12): 48-bit Address Width 0xd (ADDR_LEN_13): 52-bit Address Width 0xe (ADDR_LEN_14): 56-bit Address Width 0xf (ADDR_LEN_15): 60-bit Address Width
bits : 2 - 5 (4 bit)
access : read-write

INST_LEN : 0x0 (INST_LEN_0): 0-bit (No Instruction) 0x1 (INST_LEN_1): 4-bit Instruction 0x2 (INST_LEN_2): 8-bit Instruction 0x3 (INST_LEN_3): 16-bit Instruction
bits : 8 - 9 (2 bit)
access : read-write

WAIT_CYCLES : Wait cycles Number of wait cycles in Dual/Quad mode between control frames transmit and data reception. This value is specified as number of SPI clock cycles.
bits : 11 - 15 (5 bit)
access : read-write