CTRL

LONG_RUN_STAT

CFG

SRC_CFG

FRO_CFG

USER_SEED

LONG_RUN_CFG

STAT

DATA

RUN : TRNG work enabled signal, valid at HIGH 0x0: disable RNG module 0x1: TRNG starts working to execute a operation of reading random number
bits : 0 - 0 (1 bit)
access : read-write

LONG_RUN_FLAG : Flag of TRNG long run test 0x0: Long run never occurred. 0x1: Long run was occurred in random number sequence After TRNG being disabled or reset, this register is cleared
bits : 0 - 0 (1 bit)
access : read-only

LONG_RUN_COUNT : Counts of TRNG long run test. This value is incremented by 1 for every long run detected by TRNG. After TRNG being disabled or reset, the register is cleared.
bits : 1 - 8 (8 bit)
access : read-only

OUT_MODE : Select TRNG Output mode. 0x4: Digital TRNG direct output, ring oscillator s0 0x6: LFSR and TRNG cyclic sampling and parity generation 0x7: LFSR and TRNG cyclic sampling 0x8: LFSR ⊕ TRNG 0x9: LFSR direct output Value is limited to 0x4, 0x6, 0x7, 0x8 or 0x9 in GR551x.
bits : 0 - 3 (4 bit)
access : read-write

LFSR_XOR_SEL : In Output mode 8, select TRNG with LFSR XOR 0x4: LFSR ⊕ Ring Oscillator s0 ( the ⊕ means XOR.) Value is limited to 0x4 in GR551x.
bits : 4 - 6 (3 bit)
access : read-write

P_MODE_CFG : TRNG post-process configuration. 0x0: No post process 0x1: bit skipping 0x2: bit counting 0x3: Von-Neumann
bits : 7 - 8 (2 bit)
access : read-write

LFSR_MODE_CFG : LFSR configuration mode- 0x0: 59 bit LFSR 0x1: 128 bit LFSR
bits : 9 - 9 (1 bit)
access : read-write

LFSR_SEED_CFG : LFSR seed configuration mode, select source of LFSR seed. 0x0: LFSR seed is from the switching current s0 0x1: LFSR seed is from the switching current s1 0x2: LFSR seed is from the switching current s2 0x3: LFSR seed is from the switching current s3 0x4: LFSR seed is from the oscillator s0 0x5: LFSR seed is from the Low Frequency Sampling s0 0x6: LFSR seed is configured by users 0x7: Random numbers do not use LFSR and completely use true random mode Value is limited to 0x4 or 0x6 in GR551x.
bits : 10 - 12 (3 bit)
access : read-write

HW_INT_EN : TRNG hardware interrupt enable.
bits : 13 - 13 (1 bit)
access : read-write

LFS_EN : Low frequency sampling TRNG enabled signal. 0x0: Disabled 0x1: Enabled Reserved in GR551x.
bits : 14 - 14 (1 bit)
access : read-write

FRO_EN : Ring oscillator TRNG enabled signal. 0x0: Disabled 0x1: Enabled
bits : 15 - 15 (1 bit)
access : read-write

WAIT_TIME : The waiting time that TRNG input reaches stable. Default value is 100 time cycles.
bits : 0 - 7 (8 bit)
access : read-write

FRO_CHAIN_SEL : Selection of Chain4- Chain7 for FRO- 0x0: select long ring 0x1: select short ring
bits : 11 - 14 (4 bit)
access : read-write

CHAIN_EN : Enable signal of each Chain in ring oscillator module It is valid when FROEN is HIGH.
bits : 0 - 7 (8 bit)
access : read-write

TEST_IN : Test input signal of each Chain for FRO The default value is 1.
bits : 8 - 15 (8 bit)
access : read-write

USER_SEED : RNG seed configured by user. Write four times to user_seed[58:0] to configure a 59-bit random number.
bits : 0 - 15 (16 bit)
access : write-only

THD_LR_TEST : Threshold configuration of RNG long run test. The run which is greater or equal to this value will be detected. Default value is 26 and the maximum value is 31.
bits : 0 - 0 (1 bit)
access : read-write

LONG_RUN_THD : Test input signal of each Chain for FRO The default value is 1.
bits : 1 - 5 (5 bit)
access : read-write

READY : TRNG status flag bit, queried by CPU 0x0: TRNG output data is not valid. 0x1: TRNG output data is valid. This register is automatically cleared by hardware after READY is set HIGH. This register is automatically cleared by hardware after read DATA
bits : 0 - 0 (1 bit)
access : read-write

DATA : TRNG data This register is automatically cleared by hardware after read
bits : 0 - 31 (32 bit)
access : read-only