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UART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x70 byte (0x0)
mem_usage : registers
protection :

Registers

RX_BUF

DIV_LATCH_LOW

TX_HDG

MODEM_CTRL

LINE_STAT

MODEM_STAT

SCRATCHPAD

SHADOW_RX_BUFx

SHADOW_TX_HDGx

DIV_LATCH_HIGH

INT_EN

FIFO_ACCESS

STAT

FIFO_CTRL

INT_ID

TX_FIFO_LEVEL

RX_FIFO_LEVEL

SW_RST

SHADOW_REQ_SEND

SHADOW_BREAK_CTRL

SHADOW_DMA_MODE

SHADOW_FIFO_EN

SHADOW_RX_TRG

SHADOW_TX_TRG

HALT_TX

DMA_SW_ACK

LINE_CTRL

DIV_LATCH_FRACTION


RX_BUF

UART Receive Buffer Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX_BUF RX_BUF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_BUF

RX_BUF : Receive Buffer Register.
bits : 0 - 7 (8 bit)
access : read-only


DIV_LATCH_LOW

UART Divisor Latch (Low)Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : RX_BUF
reset_Mask : 0x0

DIV_LATCH_LOW DIV_LATCH_LOW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_LATCH_LOW

DIV_LATCH_LOW : Divisor Latch (Low).
bits : 0 - 7 (8 bit)
access : read-write


TX_HDG

UART Transmit Holding Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : DIV_LATCH_LOW
reset_Mask : 0x0

TX_HDG TX_HDG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_HDG

TX_HDG : Transmit Holding Register.
bits : 0 - 7 (8 bit)
access : write-only


MODEM_CTRL

UART Modem Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODEM_CTRL MODEM_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQ_TO_SEND LOOP_BACK

REQ_TO_SEND : Request to Send
bits : 1 - 1 (1 bit)
access : read-write

LOOP_BACK : LoopBack Bit
bits : 4 - 4 (1 bit)
access : read-write


LINE_STAT

UART Line Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LINE_STAT LINE_STAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_READY OVER_ERR PARITY_ERR FRAMING_ERR BREAK_INT TX_HDG_EMPTY TX_EMPTY RX_FIFO_ERR

DATA_READY : Data Ready bit.
bits : 0 - 0 (1 bit)
access : read-only

OVER_ERR : Overrun error bit.
bits : 1 - 1 (1 bit)
access : read-only

PARITY_ERR : Parity Error bit.
bits : 2 - 2 (1 bit)
access : read-only

FRAMING_ERR : Framing Error bit.
bits : 3 - 3 (1 bit)
access : read-only

BREAK_INT : Break Interrupt bit
bits : 4 - 4 (1 bit)
access : read-only

TX_HDG_EMPTY : Transmit Holding Register Empty bit
bits : 5 - 5 (1 bit)
access : read-only

TX_EMPTY : Transmitter Empty bit
bits : 6 - 6 (1 bit)
access : read-only

RX_FIFO_ERR : Receiver FIFO Error bit.
bits : 7 - 7 (1 bit)
access : read-only


MODEM_STAT

UART Modem Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MODEM_STAT MODEM_STAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DELTA_CLR_SEND CLR_SEND

DELTA_CLR_SEND : Delta Clear to Send.
bits : 0 - 0 (1 bit)
access : read-only

CLR_SEND : Clear to Send
bits : 4 - 4 (1 bit)
access : read-only


SCRATCHPAD

UART Scratchpad Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCHPAD SCRATCHPAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCR

SCR : This register is for programmers to use as a temporary storage space
bits : 0 - 7 (8 bit)
access : read-write


SHADOW_RX_BUFx

UART Shadow Receive Buffer Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SHADOW_RX_BUFx SHADOW_RX_BUFx read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHADOW_RX_BUFn

SHADOW_RX_BUFn : Shadow Receive Buffer Register n.
bits : 0 - 7 (8 bit)
access : read-only


SHADOW_TX_HDGx

UART Shadow Transmit Holding Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : SHADOW_RX_BUFx
reset_Mask : 0x0

SHADOW_TX_HDGx SHADOW_TX_HDGx write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHADOW_TX_HDGn

SHADOW_TX_HDGn : Shadow Transmit Holding Register n
bits : 0 - 7 (8 bit)
access : write-only


DIV_LATCH_HIGH

UART Divisor Latch High Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV_LATCH_HIGH DIV_LATCH_HIGH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLH

DLH : Divisor Latch (high).
bits : 0 - 7 (8 bit)
access : read-write


INT_EN

UART Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DIV_LATCH_HIGH
reset_Mask : 0x0

INT_EN INT_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_RX_EN INT_TX_HE INT_RX_LSE INT_MSE INT_GTHEE

INT_RX_EN : Enable Received Data Available Interrupt.
bits : 0 - 0 (1 bit)
access : read-write

INT_TX_HE : Enable Transmit Holding Register Empty Interrupt
bits : 1 - 1 (1 bit)
access : read-write

INT_RX_LSE : Enable Receiver Line Status Interrupt.
bits : 2 - 2 (1 bit)
access : read-write

INT_MSE : Enable Modem Status Interrupt.
bits : 3 - 3 (1 bit)
access : read-write

INT_GTHEE : This is used to enable/disable the generation of TX_HDG_EMPTY Interrupt
bits : 7 - 7 (1 bit)
access : read-write


FIFO_ACCESS

UART FIFO Access Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO_ACCESS FIFO_ACCESS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO_ACCESS_EN

FIFO_ACCESS_EN : This register is use to enable a FIFO access mode
bits : 0 - 0 (1 bit)
access : read-only


STAT

UART Status Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_FIFO_FULL TX_FIFO_EMPTY RX_FIFO_EMPTY RX_FIFO_FULL

TX_FIFO_FULL : Transmit FIFO Not Full
bits : 1 - 1 (1 bit)
access : read-only

TX_FIFO_EMPTY : Transmit FIFO Empty.
bits : 2 - 2 (1 bit)
access : read-only

RX_FIFO_EMPTY : Receive FIFO Not Empty.
bits : 3 - 3 (1 bit)
access : read-only

RX_FIFO_FULL : Receive FIFO Full.
bits : 4 - 4 (1 bit)
access : read-only


FIFO_CTRL

UART FIFO Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FIFO_CTRL FIFO_CTRL write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO_EN RX_FIFO_RST TX_FIFO_RST DMA_MODE TX_EMPTY_TRG RX_FIFO_TRG

FIFO_EN : FIFO Enable
bits : 0 - 0 (1 bit)
access : write-only

RX_FIFO_RST : RCVR FIFO Reset
bits : 1 - 1 (1 bit)
access : write-only

TX_FIFO_RST : XMIT FIFO Reset
bits : 2 - 2 (1 bit)
access : write-only

DMA_MODE : DMA Mode
bits : 3 - 3 (1 bit)
access : write-only

TX_EMPTY_TRG : TX Empty Trigger
bits : 4 - 5 (2 bit)
access : write-only

RX_FIFO_TRG : RCVR Trigger
bits : 6 - 7 (2 bit)
access : write-only


INT_ID

UART Interrupt Identification Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : FIFO_CTRL
reset_Mask : 0x0

INT_ID INT_ID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_PRIOR FIFO_EN

INT_PRIOR : This indicates the highest priority pending interrupt
bits : 0 - 3 (4 bit)
access : read-only

FIFO_EN : This is used to indicate whether the FIFOs are enabled or disabled.
bits : 6 - 7 (2 bit)
access : read-only


TX_FIFO_LEVEL

UART Transmit FIFO Level Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TX_FIFO_LEVEL TX_FIFO_LEVEL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_FIFO_LEVEL

TX_FIFO_LEVEL : Transmit FIFO Level.
bits : 0 - 7 (8 bit)
access : read-only


RX_FIFO_LEVEL

UART Receive FIFO Level Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX_FIFO_LEVEL RX_FIFO_LEVEL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_FIFO_LEVEL

RX_FIFO_LEVEL : Receive FIFO Level.
bits : 0 - 7 (8 bit)
access : read-only


SW_RST

UART Software Reset Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SW_RST SW_RST write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_RST RX_FIFO_RST TX_FIFO_RST

UART_RST : UART Reset
bits : 0 - 0 (1 bit)
access : write-only

RX_FIFO_RST : RCVR FIFO Reset.
bits : 1 - 1 (1 bit)
access : write-only

TX_FIFO_RST : XMIT FIFO Reset.
bits : 2 - 2 (1 bit)
access : write-only


SHADOW_REQ_SEND

UART Shadow Request to Send Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHADOW_REQ_SEND SHADOW_REQ_SEND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHADOW_REQUEST_SEND

SHADOW_REQUEST_SEND : Shadow Request to Send.
bits : 0 - 0 (1 bit)
access : read-write


SHADOW_BREAK_CTRL

UART Shadow Break Control Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHADOW_BREAK_CTRL SHADOW_BREAK_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHADOW_BREAK_CB

SHADOW_BREAK_CB : Shadow Break Control Bit.
bits : 0 - 0 (1 bit)
access : read-write


SHADOW_DMA_MODE

UART Shadow DMA Mode Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHADOW_DMA_MODE SHADOW_DMA_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHADOW_DMA_MODE

SHADOW_DMA_MODE : Shadow DMA Mode.
bits : 0 - 0 (1 bit)
access : read-write


SHADOW_FIFO_EN

UART Shadow FIFO Enable Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHADOW_FIFO_EN SHADOW_FIFO_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHADOW_FIFO_EN

SHADOW_FIFO_EN : Shadow FIFO Enable.
bits : 0 - 0 (1 bit)
access : read-write


SHADOW_RX_TRG

UART Shadow RCVR Trigger Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHADOW_RX_TRG SHADOW_RX_TRG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHADOW_RX_TRG

SHADOW_RX_TRG : Shadow RCVR Trigger.
bits : 0 - 1 (2 bit)
access : read-write


SHADOW_TX_TRG

UART Shadow TX Empty Trigger Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHADOW_TX_TRG SHADOW_TX_TRG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHADOW_TX_TRG

SHADOW_TX_TRG : Shadow TX Empty Trigger.
bits : 0 - 1 (2 bit)
access : read-write


HALT_TX

UART Halt TX Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HALT_TX HALT_TX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HALT_TX

HALT_TX : Halt TX
bits : 0 - 0 (1 bit)
access : read-write


DMA_SW_ACK

UART DMA Software Acknowledge Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DMA_SW_ACK DMA_SW_ACK write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SW_ACK

DMA_SW_ACK : DMA Software Acknowledge.
bits : 0 - 0 (1 bit)
access : write-only


LINE_CTRL

UART Line Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LINE_CTRL LINE_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_LEN_SEL STOP_BITS PARITY_EN EVEN_PARITY_SEL STICK_PARITY BREAK_CTRL_BIT DIV_LATCH_AB

DATA_LEN_SEL : Data Length Select
bits : 0 - 1 (2 bit)
access : read-write

STOP_BITS : Number of stop bits
bits : 2 - 2 (1 bit)
access : read-write

PARITY_EN : Parity Enable.
bits : 3 - 3 (1 bit)
access : read-write

EVEN_PARITY_SEL : Even Parity Select.
bits : 4 - 4 (1 bit)
access : read-write

STICK_PARITY : Stick Parity.
bits : 5 - 5 (1 bit)
access : read-write

BREAK_CTRL_BIT : Break Control Bit.
bits : 6 - 6 (1 bit)
access : read-write

DIV_LATCH_AB : Divisor Latch Access Bit
bits : 7 - 7 (1 bit)
access : read-write


DIV_LATCH_FRACTION

UART DMA Software Acknowledge Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV_LATCH_FRACTION DIV_LATCH_FRACTION read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_LATCH_FRACTION

DIV_LATCH_FRACTION : Fractional part of divisor
bits : 0 - 3 (4 bit)
access : read-write



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