CACHE_CTRL0

CACHE_STAT

CACHE_CRTL1

CACHE_HIT_COUNT

CACHE_MISS_COUNT

XIP_CTRL0

XIP_CTRL1

XIP_CTRL2

XIP_CTRL3

XIP_STAT

XIP_SOFT_RST

CACHE_EN : 0x0: Cache_enabled 0x1: Cache_disabled
bits : 0 - 0 (1 bit)
access : read-write

TAG_FLUSH_EN : Enable tag memory Flush Out of reset. Tag memory will get flushed unless tag_ret is enabled (Tag_ret signal lives in cpu register space). 0x0: Tag memory Flush is disabled 0x1: Tag memory Flush is enabled.
bits : 1 - 1 (1 bit)
access : read-write

FIFO_CLR : Clear LFU FIFO. 0x0: FIFO in Normal Mode 0x1: FIFO in Clear Mode
bits : 3 - 3 (1 bit)
access : read-write

HIT_MISS_CLR : Clear Hit/Miss Counters. 0x0: Hit/Miss Counters in Normal Mode 0x1: Hit/Miss Counters in Clear Mode
bits : 4 - 4 (1 bit)
access : read-write

STAT : Tag_flush_busy status. 0x0: Idle 0x1: Busy
bits : 0 - 0 (1 bit)
access : read-only

RD_MARGIN : Read margin
bits : 0 - 0 (1 bit)
access : read-write

WR_MARGIN : Write margin
bits : 1 - 1 (1 bit)
access : read-write

RW_MARGIN_CTRL : Read write margin control
bits : 2 - 3 (2 bit)
access : read-write

BIAS_TRIM : Bias Trim signal
bits : 4 - 7 (4 bit)
access : read-write

BUS_MUX_SRC : Select 1 of 8 debugbus configurations Debug bus is 8-bit bus.
bits : 8 - 10 (3 bit)
access : read-write

BUS_MUX_EN : Debug bus Mux Enable/Disable. 0x0: enable 0x1: disable
bits : 11 - 11 (1 bit)
access : read-write

HIT_COUNT : Hits Counter
bits : 0 - 31 (32 bit)
access : read-only

MISS_COUNT : Cache miss counter
bits : 0 - 31 (32 bit)
access : read-only

XIP_CFG_CMD : XIP configuration read command. 0x03: Read 0x0B: Fast Read 0x3B: Fast Dual Out Read 0x6B: Fast Quad Out Read 0xBB: Fast Dual I/O Read 0xEB: Fast Quad I/O Read All others reserved
bits : 0 - 7 (8 bit)
access : read-write

XIP_CFG_HPME : XIP configuration High Performance Mode. 0x0: HP mode disable 0x1: HP mode enable
bits : 0 - 0 (1 bit)
access : read-write

XIP_CFG_SS : XIP configuration slave select . 0x1: slave select 0 0x2: slave select 1 0x4: slave select 2 0x8: slave select 3 All other reserved
bits : 1 - 4 (4 bit)
access : read-write

XIP_CFG_CPHA : XIP configuration CPHA mode. 0x0: CPHA mode 0 0x1: CPHA mode 1
bits : 5 - 5 (1 bit)
access : read-write

XIP_CFG_CPOL : XIP configuration CPOL mode. 0x0: CPOL mode 0 0x1: CPOL mode 1
bits : 6 - 6 (1 bit)
access : read-write

XIP_CFG_ADDR4 : XIP configuration 4-Byte Address mode. 0x0: XIP issues 3-Byte Address 0x1: XIP issues 4-Byte SPI Address
bits : 7 - 7 (1 bit)
access : read-write

XIP_CFG_LE32 : XIP configuration 32-bit Little-Endian Arrangement of Read Data. 0x0: Read Data is Big Endian 0x1: Read Data is 32-bit Little Endian
bits : 8 - 8 (1 bit)
access : read-write

XIP_CFG_HPM : XIP Mode Command Byte. This byte is transferred from core to QSPI FLASH memory. It is the value specified by different QSPI FLASH memory vendor to enter into its status register to activate HP mode in dual I/O and Quad I/O access
bits : 0 - 7 (8 bit)
access : read-write

XIP_CFG_DC : Used to configure the number of dummy cycles used by the core for Fast Read, Fast Read Dual Output, Fast Read Quad Ouput. Fast Read Dual I/O: 4 x value + 4 Fast Read Quad I/O: 2 x value + 2 Fast Read Quad Output: 8 x value
bits : 8 - 11 (4 bit)
access : read-write

XIP_CFG_HPED : Configure the number of dummy cycles necessary to terminate high performance mode. This is used by the core when existing XIP mode after performing high-performance transfers to ensure that FLASH device is not still in HP mode. For Dual mode, this value is multiplied by 4 to get the actual number of dummy cycles. For Quad mode, this value is multiplied by 2 to get the actual number of dummy cycle
bits : 12 - 13 (2 bit)
access : read-write

XIP_EN_REQ : XIP Enable Request. 0x0: Disable XIP mode 0x1: Enable XIP mode When set to 1’b1, do not access QSPI address space. Wait until XIP_EN_OUT is 1’b1. When set to 1’b0, do not access QSPI address space. Wait until XIP_EN_OUT is 1’b0.
bits : 0 - 0 (1 bit)
access : read-write

XIP_EN_OUT : XIP Enable Status. 0x0: XIP mode is disabled 0x1: XIP mode is enabled
bits : 0 - 0 (1 bit)
access : read-only

SOFT_RST : Soft reset IP by writing 1’b0, internal logic generates active low reset for one HCLK cycle
bits : 0 - 0 (1 bit)
access : read-write