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I2C

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR1

TIMINGR

TIMEOUTR

ISR

ICR

PECR

RXDR

TXDR

CR2

OAR1

OAR2


CR1

Control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PE TXIE RXIE ADDRE NACKIE STOPIE TCIE ERRIE DNF ANFOFF TCDMAEN RXDMAEN SBC NOSTRETCH WUPEN GCEN SMBHEN SMBDEN ALERTEN PECEN

PE : Peripheral enable
bits : 0 - 0 (1 bit)

TXIE : TXIE
bits : 1 - 1 (1 bit)

RXIE : RXIE
bits : 2 - 2 (1 bit)

ADDRE : ADDRE
bits : 3 - 3 (1 bit)

NACKIE : NACKIE
bits : 4 - 4 (1 bit)

STOPIE : STOPIE
bits : 5 - 5 (1 bit)

TCIE : TCIE
bits : 6 - 6 (1 bit)

ERRIE : ERRIE
bits : 7 - 7 (1 bit)

DNF : DNF
bits : 8 - 11 (4 bit)

ANFOFF : ANFOFF
bits : 12 - 12 (1 bit)

TCDMAEN : TCDMAEN
bits : 14 - 14 (1 bit)

RXDMAEN : RXDMAEN
bits : 15 - 15 (1 bit)

SBC : SBC
bits : 16 - 16 (1 bit)

NOSTRETCH : NOSTRETCH
bits : 17 - 17 (1 bit)

WUPEN : WUPEN
bits : 18 - 18 (1 bit)

GCEN : GCEN
bits : 19 - 19 (1 bit)

SMBHEN : SMBHEN
bits : 20 - 20 (1 bit)

SMBDEN : SMBDEN
bits : 21 - 21 (1 bit)

ALERTEN : ALERTEN
bits : 22 - 22 (1 bit)

PECEN : PECEN
bits : 23 - 23 (1 bit)


TIMINGR

Timing register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMINGR TIMINGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCLL SCLH SDADEL SCLDEL PRESC

SCLL : SCLL
bits : 0 - 7 (8 bit)

SCLH : SCLH
bits : 8 - 15 (8 bit)

SDADEL : SDADEL
bits : 16 - 19 (4 bit)

SCLDEL : SCLDEL
bits : 20 - 23 (4 bit)

PRESC : PRESC
bits : 28 - 31 (4 bit)


TIMEOUTR

Timeout register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMEOUTR TIMEOUTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMEOUTA TIDLE TIMOUTEN TIMEOUTB TEXTEN

TIMEOUTA : TIMEOUTA
bits : 0 - 11 (12 bit)

TIDLE : TIDLE
bits : 12 - 12 (1 bit)

TIMOUTEN : TIMOUTEN
bits : 15 - 15 (1 bit)

TIMEOUTB : TIMEOUTB
bits : 16 - 27 (12 bit)

TEXTEN : TEXTEN
bits : 31 - 31 (1 bit)


ISR

Interrupt and Status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXE TXIS RXNE ADDR NACKF STOPF TC TCR BERR ARLO OVR PECERR TIMEOUT ALERT BUSY DIR ADDCODE

TXE : TXE
bits : 0 - 0 (1 bit)
access : read-write

TXIS : TXIS
bits : 1 - 1 (1 bit)
access : read-write

RXNE : RXNE
bits : 2 - 2 (1 bit)
access : read-only

ADDR : ADDR
bits : 3 - 3 (1 bit)
access : read-only

NACKF : NACKF
bits : 4 - 4 (1 bit)
access : read-only

STOPF : STOPF
bits : 5 - 5 (1 bit)
access : read-only

TC : TC
bits : 6 - 6 (1 bit)
access : read-only

TCR : TCR
bits : 7 - 7 (1 bit)
access : read-only

BERR : BERR
bits : 8 - 8 (1 bit)
access : read-only

ARLO : ARLO
bits : 9 - 9 (1 bit)
access : read-only

OVR : OVR
bits : 10 - 10 (1 bit)
access : read-only

PECERR : PECERR
bits : 11 - 11 (1 bit)
access : read-only

TIMEOUT : TIMEOUT
bits : 12 - 12 (1 bit)
access : read-only

ALERT : ALERT
bits : 13 - 13 (1 bit)
access : read-only

BUSY : BUSY
bits : 15 - 15 (1 bit)
access : read-only

DIR : DIR
bits : 16 - 16 (1 bit)
access : read-only

ADDCODE : ADDCODE
bits : 17 - 23 (7 bit)
access : read-only


ICR

Interrupt clear register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRCF NACKCF STOPCF BERRCF ARLOCF OVRCF PECCF TIMOUTCF ALERTC

ADDRCF : ADDRCF
bits : 3 - 3 (1 bit)

NACKCF : NACKCF
bits : 4 - 4 (1 bit)

STOPCF : STOPCF
bits : 5 - 5 (1 bit)

BERRCF : BERRCF
bits : 8 - 8 (1 bit)

ARLOCF : ARLOCF
bits : 9 - 9 (1 bit)

OVRCF : OVRCF
bits : 10 - 10 (1 bit)

PECCF : PECCF
bits : 11 - 11 (1 bit)

TIMOUTCF : TIMOUTCF
bits : 12 - 12 (1 bit)

ALERTC : ALERTC
bits : 13 - 13 (1 bit)


PECR

PEC register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PECR PECR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEC

PEC : PEC
bits : 0 - 7 (8 bit)


RXDR

Receive data register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDR RXDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : RXDATA
bits : 0 - 7 (8 bit)


TXDR

Transmit data register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXDR TXDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : TXDATA
bits : 0 - 7 (8 bit)


CR2

Control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SADD0 SADD1_7 SADD8_9 RD_WRN ADD10 HEAD10R START STOP NACK NBYTES RELOAD AUTOEND PECBYTE

SADD0 : Slave address bit 0
bits : 0 - 0 (1 bit)

SADD1_7 : Slave address bit 7_1
bits : 1 - 7 (7 bit)

SADD8_9 : Slave address bit 8_9
bits : 8 - 9 (2 bit)

RD_WRN : Transfer direction
bits : 10 - 10 (1 bit)

ADD10 : 10-bit addressing mode
bits : 11 - 11 (1 bit)

HEAD10R : 10-bit address header only read direction
bits : 12 - 12 (1 bit)

START : Start generation
bits : 13 - 13 (1 bit)

STOP : Stop generation
bits : 14 - 14 (1 bit)

NACK : NACK generation
bits : 15 - 15 (1 bit)

NBYTES : Number of bytes
bits : 16 - 23 (8 bit)

RELOAD : NBYTES reload mode
bits : 24 - 24 (1 bit)

AUTOEND : Automatic end mode
bits : 25 - 25 (1 bit)

PECBYTE : Packet error checking byte
bits : 26 - 26 (1 bit)


OAR1

Own address register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OAR1 OAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OA1 OA11_7 OA18_9 OA1MODE OA1EN

OA1 : OA1
bits : 0 - 0 (1 bit)

OA11_7 : OA11_7
bits : 1 - 7 (7 bit)

OA18_9 : OA18_9
bits : 8 - 9 (2 bit)

OA1MODE : OA1MODE
bits : 10 - 10 (1 bit)

OA1EN : OA1EN
bits : 15 - 15 (1 bit)


OAR2

Own address register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OAR2 OAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OA21_7 OA2MSK OA2EN

OA21_7 : OA21_7
bits : 1 - 7 (7 bit)

OA2MSK : OA2MSK
bits : 8 - 10 (3 bit)

OA2EN : OA2EN
bits : 15 - 15 (1 bit)



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