\n

UART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

UART_URDR

UART_URSIFR

UART_URDLR

UART_URTSTR

UART_URCR

UART_URIER


UART_URDR

UART_URDR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART_URDR UART_URDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB

DB : DB
bits : 0 - 8 (9 bit)
access : read-write


UART_URSIFR

UART_URSIFR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART_URSIFR UART_URSIFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OEI PEI FEI BII RXDR TXDE TXC

OEI : OEI
bits : 1 - 2 (2 bit)
access : read-write

PEI : PEI
bits : 2 - 4 (3 bit)
access : read-write

FEI : FEI
bits : 3 - 6 (4 bit)
access : read-write

BII : BII
bits : 4 - 8 (5 bit)
access : read-write

RXDR : RXDR
bits : 5 - 10 (6 bit)
access : read-write

TXDE : TXDE
bits : 7 - 14 (8 bit)
access : read-write

TXC : TXC
bits : 8 - 16 (9 bit)
access : read-write


UART_URDLR

UART_URDLR
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART_URDLR UART_URDLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRD

BRD : BRD
bits : 0 - 15 (16 bit)
access : read-write


UART_URTSTR

UART_URTSTR
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART_URTSTR UART_URTSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBM

LBM : LBM
bits : 0 - 1 (2 bit)
access : read-write


UART_URCR

UART_URCR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART_URCR UART_URCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRSM URTXEN URRXEN TXDMAEN RXDMAEN WLS NSB PBE EPE SPE BCB

TRSM : TRSM
bits : 2 - 4 (3 bit)
access : read-write

URTXEN : URTXEN
bits : 4 - 8 (5 bit)
access : read-write

URRXEN : URRXEN
bits : 5 - 10 (6 bit)
access : read-write

TXDMAEN : TXDMAEN
bits : 6 - 12 (7 bit)
access : read-write

RXDMAEN : RXDMAEN
bits : 7 - 14 (8 bit)
access : read-write

WLS : WLS
bits : 8 - 17 (10 bit)
access : read-write

NSB : NSB
bits : 10 - 20 (11 bit)
access : read-write

PBE : PBE
bits : 11 - 22 (12 bit)
access : read-write

EPE : EPE
bits : 12 - 24 (13 bit)
access : read-write

SPE : SPE
bits : 13 - 26 (14 bit)
access : read-write

BCB : BCB
bits : 14 - 28 (15 bit)
access : read-write


UART_URIER

UART_URIER
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UART_URIER UART_URIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDRIE TXDEIE TXCIE OEIE PEIE FEIE BIE

RXDRIE : RXDRIE
bits : 0 - 0 (1 bit)
access : read-write

TXDEIE : TXDEIE
bits : 1 - 2 (2 bit)
access : read-write

TXCIE : TXCIE
bits : 2 - 4 (3 bit)
access : read-write

OEIE : OEIE
bits : 3 - 6 (4 bit)
access : read-write

PEIE : PEIE
bits : 4 - 8 (5 bit)
access : read-write

FEIE : FEIE
bits : 5 - 10 (6 bit)
access : read-write

BIE : BIE
bits : 6 - 12 (7 bit)
access : read-write



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