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address_offset : 0x0 Bytes (0x0)
size : 0xF2 byte (0x0)
mem_usage : registers
protection :
Hardware Reset control register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISABLE_HWR : Disables the RST functionality on P00
bits : 0 - 0 (1 bit)
access : read-write
Hibernation control register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIBERNATION_ENABLE : Enables the hibernation mode when sleeping 0: deep sleep mode, PD_SLP remains on 1: hibernation mode, PD_SLP goes off. REMAP_ADR0 needs to be set to the correct source to boot from before going to sleep.
bits : 0 - 0 (1 bit)
access : read-write
HIBERN_WKUP_POLARITY : Selects the polarity of the wakeup source. The polarity must be chosen such that the ANA_STATUS_REG[CLKLESS_WAKEUP_STAT] is '1'. Any change on the selected GPIOs will make the CLKLESS_WAKEUP_STAT go to '0', and wakeup the system from hibernation.
bits : 1 - 2 (2 bit)
access : read-write
HIBERN_WKUP_MASK : Selects which pin to wakeup from
bits : 2 - 8 (7 bit)
access : read-write
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBAT_HL_CONNECT_RES_CTRL : 00: OFF 01: Forced ON 10: Active: automatic control, Sleep: forced ON 11: Automatic control
bits : 0 - 1 (2 bit)
access : read-write
POR_VBAT_LOW_RST_MASK : Mask rst from por_vbat_low
bits : 2 - 4 (3 bit)
access : read-write
POR_VBAT_HIGH_RST_MASK : Mask rst from por_vbat_high
bits : 3 - 6 (4 bit)
access : read-write
RC32K_HIGH_SPEED_FORCE :
bits : 4 - 8 (5 bit)
access : read-write
RC32K_LOW_SPEED_FORCE :
bits : 5 - 10 (6 bit)
access : read-write
CHARGE_VBAT_DISABLE : Do not charge vbat high in boost mode
bits : 6 - 12 (7 bit)
access : read-write
BOOST_MODE_FORCE : 0x:automatic selection of boost mode 11: force boost mode 10: force buck mode
bits : 7 - 15 (9 bit)
access : read-write
CMP_VCONT_SLP_DISABLE : Disable vcont comparator in SLP
bits : 9 - 18 (10 bit)
access : read-write
LDO_RET_TRIM : VDD clamp level setting for hibernation mode
bits : 10 - 23 (14 bit)
access : read-write
FORCE_RUNNING_COMP_DIS :
bits : 14 - 28 (15 bit)
access : read-write
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_GP_DATA :
bits : 0 - 3 (4 bit)
access : read-write
DISABLE_CLAMP_OVERRULE :
bits : 4 - 8 (5 bit)
access : read-write
ANA_SPARE :
bits : 5 - 12 (8 bit)
access : read-write
Reset status register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORESET_STAT : Indicates that a PowerOn Reset has happened
bits : 0 - 0 (1 bit)
access : read-write
HWRESET_STAT : Indicates that a HW Reset has happened This bit is also set with a PowerOn Reset
bits : 1 - 2 (2 bit)
access : read-write
SWRESET_STAT : Indicates that a SW Reset has been requested. The SW reset is requested by SYS_CTRL_REG[SW_RESET] or SCB->AIRCR inside the ARM. This bit is also set with a PowerOn Reset
bits : 2 - 4 (3 bit)
access : read-write
WDOGRESET_STAT : Indicates that a Watchdog has happened. This bit is also set with a PowerOn Reset
bits : 3 - 6 (4 bit)
access : read-write
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMx_LPMX : RAM[3:1] Transparent Light Sleep (TLS) Core Enable for System RAMs. Assert low to enable the TLS core feature, which will result in lower leakage current. In case VDD is below 0.81V, it is necessary to hold this pin high to maintain data retention.
bits : 0 - 2 (3 bit)
access : read-write
Control the state retention of the GPIO ports
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAD_LATCH_EN : Controls the state retention of the pads. 0: latches are closed, pads retain their state. 1: latches are open, new control values have immediate effect
bits : 0 - 0 (1 bit)
access : read-write
address_offset : 0xF0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEST_VDD :
bits : 0 - 0 (1 bit)
access : read-write
LDOS_DISABLE :
bits : 1 - 2 (2 bit)
access : read-write
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