SET_FREEZE_REG

RESET_FREEZE_REG

DEBUG_REG

GP_STATUS_REG

GP_CONTROL_REG

BLE_TIMER_REG

MEM_CTRL_REG

FRZ_WKUPTIM : If '1', the Wake Up Timer is frozen, '0' is discarded.
bits : 0 - 0 (1 bit)
access : read-write

FRZ_SWTIM : If '1', the SW Timer (TIMER0) is frozen, '0' is discarded.
bits : 1 - 2 (2 bit)
access : read-write

FRZ_BLETIM : If '1', the BLE master clock is frozen, '0' is discarded.
bits : 2 - 4 (3 bit)
access : read-write

FRZ_WDOG : If '1', the watchdog timer is frozen, '0' is discarded. WATCHDOG_CTRL_REG[NMI_RST] must be '0' to allow the freeze function.
bits : 3 - 6 (4 bit)
access : read-write

FRZ_DMA : If '1', the DMA is frozen, '0' is discarded.
bits : 4 - 8 (5 bit)
access : read-write

FRZ_WKUPTIM : If '1', the Wake Up Timer continues, '0' is discarded.
bits : 0 - 0 (1 bit)
access : read-write

FRZ_SWTIM : If '1', the SW Timer (TIMER0) continues, '0' is discarded.
bits : 1 - 2 (2 bit)
access : read-write

FRZ_BLETIM : If '1', the the BLE master clock continues, '0' is discarded.
bits : 2 - 4 (3 bit)
access : read-write

FRZ_WDOG : If '1', the watchdog timer continues, '0' is discarded.
bits : 3 - 6 (4 bit)
access : read-write

FRZ_DMA : If '1', the DMA continues, '0' is discarded.
bits : 4 - 8 (5 bit)
access : read-write

DEBUGS_FREEZE_EN : Default '1', freezing of the on-chip timers is enabled when the Cortex-M0Plus is halted in DEBUG State. If '0', freezing of the on-chip timers is depending on FREEZE_REG when the Cortex-M0Plus is halted in DEBUG State except the watchdog timer. The watchdog timer is always frozen when the Cortex-M0Plus is halted in DEBUG State.
bits : 0 - 0 (1 bit)
access : read-write

CAL_PHASE : If '1', it designates that the chip is in Calibration Phase i.e. the OTP has been initially programmed but no Calibration has occured.
bits : 0 - 0 (1 bit)
access : read-write

BLE_WAKEUP_REQ : If '1', the BLE wakes up. Must be kept high at least for 1 low power clock period. If the BLE is in deep sleep state, then by setting this bit it will cause the wakeup LP IRQ to be asserted with a delay of 3 to 4 low power cycles.
bits : 0 - 0 (1 bit)
access : read-write

BLE_WAKEUP_LP_IRQ : The current value of the BLE_WAKEUP_LP_IRQ interrupt request.
bits : 2 - 4 (3 bit)
access : read-only

CPU_DMA_BUS_PRIO : Controls the CPU DMA system bus priority: If '0', the CPU has highest priority. If '1', the DMA has highest priority.
bits : 4 - 8 (5 bit)
access : read-write

BLE_TIMER_DATA_CTRL : Refer to BLE_TIMER_REG.
bits : 5 - 11 (7 bit)
access : read-write

BLE_TIMER_DATA : Operation depends on GP_CONTROL_REG->BLE_TIMER_DATA_CTRL. If BLE_TIMER_DATA_CTRL = 0 then: This register is located at the Always On Power Domain and it holds the automatically sampled value of the BLE FINECNT timer The HW automatically samples the value into this register during the sequence of BLE Sleep On and restores automatically the value during the BLE Wake up sequence. The Software may read and modify the value while the BLE is in Sleep state. While the BLE is awake, the value of the register has no meaning, while changing the value by writing another one will have no effect in the operation of the BLE core. There is a constraint when the SW performs an write-read sequence where it has to inject a one cycle delay in between (e.g. write-NOP-read) in order to read back the correct value. If BLE_TIMER_DATA_CTRL is non 0 then write operations have the same effect as when BLE_TIMER_DATA_CTRL=0, while for read operations: BLE_TIMER_DATA_CTRL= 1: then reading BLE_TIMER_REG returns deepsldur[9:0] . BLE_TIMER_DATA_CTRL= 2: then reading BLE_TIMER_REG returns deepsltime_samp[9:0] . BLE_TIMER_DATA_CTRL= 3: then reading BLE_TIMER_REG returns {deep_sleep_stat_monitor, deepsltime_samp[18:10]}. .
bits : 0 - 9 (10 bit)
access : read-write

ROM_MARGIN_CTRL :
bits : 0 - 3 (4 bit)
access : read-write

ROM_MARGIN_EN :
bits : 4 - 8 (5 bit)
access : read-write

RAM_DST :
bits : 5 - 10 (6 bit)
access : read-write

RAM_MARGIN :
bits : 6 - 13 (8 bit)
access : read-write

ARB1_AHB_WR_BUFF :
bits : 8 - 16 (9 bit)
access : read-only

ARB1_AHB2_WR_BUFF :
bits : 9 - 18 (10 bit)
access : read-only

ARB2_AHB_WR_BUFF :
bits : 10 - 20 (11 bit)
access : read-only

ARB2_AHB2_WR_BUFF :
bits : 11 - 22 (12 bit)
access : read-only