QDEC_CTRL_REG

QDEC_XCNT_REG

QDEC_YCNT_REG

QDEC_CLOCKDIV_REG

QDEC_CTRL2_REG

QDEC_ZCNT_REG

QDEC_EVENT_CNT_REG

QDEC_IRQ_ENABLE : 0 = interrupt is masked 1 = interrupt is enabled
bits : 0 - 0 (1 bit)
access : read-write

QDEC_EVENT_CNT_CLR : Writing 1 QDEC_EVENT_CNT_REG is cleared
bits : 1 - 2 (2 bit)
access : read-write

QDEC_IRQ_STATUS : 1 = Interrupt is occured. 0 = No interrupt pending Write 1 will clear the pending interrupt
bits : 2 - 4 (3 bit)
access : read-write

QDEC_IRQ_THRES : Defines the number of events on either counter (X or Y or Z) that need to be reached before an interrupt is generated. Events are equal to QDEC_IRQ_THRES+1.
bits : 3 - 13 (11 bit)
access : read-write

QDEC_X_CNT : Contains a signed value of the events. Zero when channel is disabled
bits : 0 - 15 (16 bit)
access : read-only

QDEC_Y_CNT : Contains a signed value of the events. Zero when channel is disabled
bits : 0 - 15 (16 bit)
access : read-only

QDEC_CLOCKDIV : Contains the number of the input clock cycles minus one, that are required to generate one logic clock cycle. Clock divider is bypassed when system runs at LP_CLK
bits : 0 - 9 (10 bit)
access : read-write

QDEC_PRESCALER_EN : 0 = no prescaler enabled 1 = in sleep and active mode, quadrature clock is divided by 2
bits : 10 - 20 (11 bit)
access : read-write

QDEC_CHX_PORT_SEL : Defines which GPIOs are mapped on Channel X 0: none 1: P0[2] -> CHX_A, P0[5] -> CHX_B 2: P0[1] -> CHX_A, P0[4] -> CHX_B 3: P0[3] -> CHX_A, P0[10] -> CHX_B 4: P0[6] -> CHX_A, P0[7] -> CHX_B 5: P0[8] -> CHX_A, P0[9] -> CHX_B 6: P0[0] -> CHX_A, P0[11] -> CHX_B 7: none
bits : 0 - 2 (3 bit)
access : read-write

QDEC_CHY_PORT_SEL : Defines which GPIOs are mapped on Channel Y 0: none 1: P0[2] -> CHY_A, P0[5] -> CHY_B 2: P0[1] -> CHY_A, P0[4] -> CHY_B 3: P0[3] -> CHY_A, P0[10] -> CHY_B 4: P0[6] -> CHY_A, P0[7] -> CHY_B 5: P0[8] -> CHY_A, P0[9] -> CHY_B 6: P0[0] -> CHY_A, P0[11] -> CHY_B 7: none
bits : 3 - 8 (6 bit)
access : read-write

QDEC_CHZ_PORT_SEL : Defines which GPIOs are mapped on Channel Z 0: none 1: P0[2] -> CHZ_A, P0[5] -> CHZ_B 2: P0[1] -> CHZ_A, P0[4] -> CHZ_B 3: P0[3] -> CHZ_A, P0[10] -> CHZ_B 4: P0[6] -> CHZ_A, P0[7] -> CHZ_B 5: P0[8] -> CHZ_A, P0[9] -> CHZ_B 6: P0[0] -> CHZ_A, P0[11] -> CHZ_B 7: none
bits : 6 - 14 (9 bit)
access : read-write

QDEC_CHX_EVENT_MODE : 0 = Normal quadrature counting 1 = Counts rising and falling edge of both ports (if both ports change at the same time, counter increases by 1)
bits : 9 - 18 (10 bit)
access : read-write

QDEC_CHY_EVENT_MODE : 0 = Normal quadrature counting 1 = Counts rising and falling edge of both ports (if both ports change at the same time, counter increases by 1)
bits : 10 - 20 (11 bit)
access : read-write

QDEC_CHZ_EVENT_MODE : 0 = Normal quadrature counting 1 = Counts rising and falling edge of both ports (if both ports change at the same time, counter increases by 1)
bits : 11 - 22 (12 bit)
access : read-write

QDEC_Z_CNT : Contains a signed value of the events. Zero when channel is disabled
bits : 0 - 15 (16 bit)
access : read-only

QDEC_EVENT_CNT : Gives the number of events at all channels.
bits : 0 - 7 (8 bit)
access : read-only