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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

ADC_CR (CR)

ADC_STR (STR)

ADC_DR0 (DR0)

ADC_DR1 (DR1)

ADC_DR2 (DR2)

ADC_DR3 (DR3)

ADC_LST0 (LST0)

ADC_DR4 (DR4)

ADC_DR5 (DR5)

ADC_DR6 (DR6)

ADC_DR7 (DR7)

ADC_TCR (TCR)

ADC_TSR (TSR)

ADC_WCR (WCR)

ADC_TR (TR)

ADC_LST1 (LST1)

ADC_IER (IER)

ADC_IRAW (IRAW)

ADC_ISR (ISR)

ADC_ICLR (ICLR)

ADC_DMAR (DMAR)

ADC_VREFCR (VREFCR)

ADC_VREFVALR (VREFVALR)


ADC_CR (CR)

ADC_CR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CR ADC_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADMODE ADCRST ADCEN ADSEQL ADSUBL

ADMODE : ADMODE
bits : 0 - 1 (2 bit)
access : read-write

ADCRST : ADCRST
bits : 6 - 12 (7 bit)
access : read-write

ADCEN : ADCEN
bits : 7 - 14 (8 bit)
access : read-write

ADSEQL : ADSEQL
bits : 8 - 18 (11 bit)
access : read-write

ADSUBL : ADSUBL
bits : 16 - 34 (19 bit)
access : read-write


ADC_STR (STR)

ADC_STR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STR ADC_STR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADST

ADST : ADST
bits : 0 - 7 (8 bit)
access : read-write


ADC_DR0 (DR0)

ADC_DR0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR0 ADC_DR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD0 ADVLD0

ADD0 : ADD0
bits : 0 - 15 (16 bit)
access : read-write

ADVLD0 : ADVLD0
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR1 (DR1)

ADC_DR1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR1 ADC_DR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD1 ADVLD1

ADD1 : ADD1
bits : 0 - 15 (16 bit)
access : read-write

ADVLD1 : ADVLD1
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR2 (DR2)

ADC_DR2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR2 ADC_DR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD2 ADVLD2

ADD2 : ADD2
bits : 0 - 15 (16 bit)
access : read-write

ADVLD2 : ADVLD2
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR3 (DR3)

ADC_DR3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR3 ADC_DR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD3 ADVLD3

ADD3 : ADD3
bits : 0 - 15 (16 bit)
access : read-write

ADVLD3 : ADVLD3
bits : 31 - 62 (32 bit)
access : read-write


ADC_LST0 (LST0)

ADC_LST0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_LST0 ADC_LST0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADSEQ0 ADSEQ1 ADSEQ2 ADSEQ3

ADSEQ0 : ADSEQ0
bits : 0 - 4 (5 bit)
access : read-write

ADSEQ1 : ADSEQ1
bits : 8 - 20 (13 bit)
access : read-write

ADSEQ2 : ADSEQ2
bits : 16 - 36 (21 bit)
access : read-write

ADSEQ3 : ADSEQ3
bits : 24 - 52 (29 bit)
access : read-write


ADC_DR4 (DR4)

ADC_DR4
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR4 ADC_DR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD4 ADVLD4

ADD4 : ADD4
bits : 0 - 15 (16 bit)
access : read-write

ADVLD4 : ADVLD4
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR5 (DR5)

ADC_DR5
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR5 ADC_DR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD5 ADVLD5

ADD5 : ADD5
bits : 0 - 15 (16 bit)
access : read-write

ADVLD5 : ADVLD5
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR6 (DR6)

ADC_DR6
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR6 ADC_DR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD6 ADVLD6

ADD6 : ADD6
bits : 0 - 15 (16 bit)
access : read-write

ADVLD6 : ADVLD6
bits : 31 - 62 (32 bit)
access : read-write


ADC_DR7 (DR7)

ADC_DR7
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DR7 ADC_DR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD7 ADVLD7

ADD7 : ADD7
bits : 0 - 15 (16 bit)
access : read-write

ADVLD7 : ADVLD7
bits : 31 - 62 (32 bit)
access : read-write


ADC_TCR (TCR)

ADC_TCR
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_TCR ADC_TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADSW ADEXTI TM0 TM1 CMP

ADSW : ADSW
bits : 0 - 0 (1 bit)
access : read-write

ADEXTI : ADEXTI
bits : 1 - 2 (2 bit)
access : read-write

TM0 : TM0
bits : 2 - 4 (3 bit)
access : read-write

TM1 : TM1
bits : 3 - 6 (4 bit)
access : read-write

CMP : CMP
bits : 4 - 8 (5 bit)
access : read-write


ADC_TSR (TSR)

ADC_TSR
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_TSR ADC_TSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADSC ADEXTIS TM0S TM1S[0] CMPS TM1S[2_1] TM0E TM1E

ADSC : ADSC
bits : 0 - 0 (1 bit)
access : read-write

ADEXTIS : ADEXTIS
bits : 8 - 19 (12 bit)
access : read-write

TM0S : TM0S
bits : 16 - 34 (19 bit)
access : read-write

TM1S[0] : TM1S[0]
bits : 19 - 38 (20 bit)
access : read-write

CMPS : CMPS
bits : 20 - 40 (21 bit)
access : read-write

TM1S[2_1] : TM1S[2:1]
bits : 22 - 45 (24 bit)
access : read-write

TM0E : TM0E
bits : 24 - 50 (27 bit)
access : read-write

TM1E : TM1E
bits : 27 - 56 (30 bit)
access : read-write


ADC_WCR (WCR)

ADC_WCR
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_WCR ADC_WCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADWLE ADWUE ADWALL ADWCH ADLCH ADUCH

ADWLE : ADWLE
bits : 0 - 0 (1 bit)
access : read-write

ADWUE : ADWUE
bits : 1 - 2 (2 bit)
access : read-write

ADWALL : ADWALL
bits : 2 - 4 (3 bit)
access : read-write

ADWCH : ADWCH
bits : 8 - 19 (12 bit)
access : read-write

ADLCH : ADLCH
bits : 16 - 35 (20 bit)
access : read-write

ADUCH : ADUCH
bits : 24 - 51 (28 bit)
access : read-write


ADC_TR (TR)

ADC_TR
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_TR ADC_TR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADLT ADUT

ADLT : ADLT
bits : 0 - 11 (12 bit)
access : read-write

ADUT : ADUT
bits : 16 - 43 (28 bit)
access : read-write


ADC_LST1 (LST1)

ADC_LST1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_LST1 ADC_LST1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADSEQ4 ADSEQ5 ADSEQ6 ADSEQ7

ADSEQ4 : ADSEQ4
bits : 0 - 4 (5 bit)
access : read-write

ADSEQ5 : ADSEQ5
bits : 8 - 20 (13 bit)
access : read-write

ADSEQ6 : ADSEQ6
bits : 16 - 36 (21 bit)
access : read-write

ADSEQ7 : ADSEQ7
bits : 24 - 52 (29 bit)
access : read-write


ADC_IER (IER)

ADC_IMR
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_IER ADC_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADIES ADIEG ADIEC ADIEL ADIEU ADIEO

ADIES : ADIES
bits : 0 - 0 (1 bit)
access : read-write

ADIEG : ADIEG
bits : 1 - 2 (2 bit)
access : read-write

ADIEC : ADIEC
bits : 2 - 4 (3 bit)
access : read-write

ADIEL : ADIEL
bits : 16 - 32 (17 bit)
access : read-write

ADIEU : ADIEU
bits : 17 - 34 (18 bit)
access : read-write

ADIEO : ADIEO
bits : 24 - 48 (25 bit)
access : read-write


ADC_IRAW (IRAW)

ADC_IRAW
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_IRAW ADC_IRAW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADIRAWS ADIRAWG ADIRAWC ADIRAWL ADIRAWU ADIRAWO

ADIRAWS : ADIRAWS
bits : 0 - 0 (1 bit)
access : read-write

ADIRAWG : ADIRAWG
bits : 1 - 2 (2 bit)
access : read-write

ADIRAWC : ADIRAWC
bits : 2 - 4 (3 bit)
access : read-write

ADIRAWL : ADIRAWL
bits : 16 - 32 (17 bit)
access : read-write

ADIRAWU : ADIRAWU
bits : 17 - 34 (18 bit)
access : read-write

ADIRAWO : ADIRAWO
bits : 24 - 48 (25 bit)
access : read-write


ADC_ISR (ISR)

ADC_ISR
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_ISR ADC_ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADISRS ADISRG ADISRC ADISRL ADISRU ADISRO

ADISRS : ADISRS
bits : 0 - 0 (1 bit)
access : read-write

ADISRG : ADISRG
bits : 1 - 2 (2 bit)
access : read-write

ADISRC : ADISRC
bits : 2 - 4 (3 bit)
access : read-write

ADISRL : ADISRL
bits : 16 - 32 (17 bit)
access : read-write

ADISRU : ADISRU
bits : 17 - 34 (18 bit)
access : read-write

ADISRO : ADISRO
bits : 24 - 48 (25 bit)
access : read-write


ADC_ICLR (ICLR)

ADC_ICLR
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_ICLR ADC_ICLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADICLRS ADICLRG ADICLRC ADICLRL ADICLRU ADICLRO

ADICLRS : ADICLRS
bits : 0 - 0 (1 bit)
access : read-write

ADICLRG : ADICLRG
bits : 1 - 2 (2 bit)
access : read-write

ADICLRC : ADICLRC
bits : 2 - 4 (3 bit)
access : read-write

ADICLRL : ADICLRL
bits : 16 - 32 (17 bit)
access : read-write

ADICLRU : ADICLRU
bits : 17 - 34 (18 bit)
access : read-write

ADICLRO : ADICLRO
bits : 24 - 48 (25 bit)
access : read-write


ADC_DMAR (DMAR)

ADC_DMAR
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DMAR ADC_DMAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDMAS ADDMAG ADDMAC

ADDMAS : ADDMAS
bits : 0 - 0 (1 bit)
access : read-write

ADDMAG : ADDMAG
bits : 1 - 2 (2 bit)
access : read-write

ADDMAC : ADDMAC
bits : 2 - 4 (3 bit)
access : read-write


ADC_VREFCR (VREFCR)

ADC_VREFCR
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_VREFCR ADC_VREFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREFEN VREFSEL MVDDAEN

VREFEN : VREFEN
bits : 0 - 0 (1 bit)
access : read-write

VREFSEL : VREFSEL
bits : 4 - 9 (6 bit)
access : read-write

MVDDAEN : MVDDAEN
bits : 8 - 16 (9 bit)
access : read-write


ADC_VREFVALR (VREFVALR)

ADC_VREFVALR
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_VREFVALR ADC_VREFVALR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREFVAL

VREFVAL : VREFEN
bits : 0 - 6 (7 bit)
access : read-write



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