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PWM0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

PWM_CNTCFR

PWM_CTR

PWM_MDCFR

PWM_CH0OCFR

PWM_CH1OCFR

PWM_CH2OCFR

PWM_CH3OCFR

PWM_CHCTR

PWM_CHPOLR

PWM_DICTR

PWM_EVGR

PWM_INTSR

PWM_TRCFR

PWM_CNTR

PWM_PSCR

PWM_CRR

PWM_CH0CR

PWM_CH1CR (PWM_CH1CCR)

PWM_CH2CR

PWM_CH3CR

PWM_CH0ACR

PWM_CH1ACR

PWM_CH2ACR

PWM_CH3ACR


PWM_CNTCFR

PWM_CNTCFR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CNTCFR PWM_CNTCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEVDIS UGDIS CMSEL DIR

UEVDIS : UEVDIS
bits : 0 - 0 (1 bit)
access : read-write

UGDIS : UGDIS
bits : 1 - 2 (2 bit)
access : read-write

CMSEL : CMSEL
bits : 16 - 33 (18 bit)
access : read-write

DIR : DIR
bits : 24 - 48 (25 bit)
access : read-write


PWM_CTR

PWM_CTR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CTR PWM_CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TME CRBE CHCCDS

TME : TME
bits : 0 - 0 (1 bit)
access : read-write

CRBE : CRBE
bits : 1 - 2 (2 bit)
access : read-write

CHCCDS : CHCCDS
bits : 16 - 32 (17 bit)
access : read-write


PWM_MDCFR

PWM_MDCFR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_MDCFR PWM_MDCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSE SMSEL MMSEL SPMSET

TSE : TSE
bits : 0 - 0 (1 bit)
access : read-write

SMSEL : SMSEL
bits : 8 - 18 (11 bit)
access : read-write

MMSEL : MMSEL
bits : 16 - 34 (19 bit)
access : read-write

SPMSET : SPMSET
bits : 24 - 48 (25 bit)
access : read-write


PWM_CH0OCFR

PWM_CH0OCFR
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CH0OCFR PWM_CH0OCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0OM[2_0] CH0PRE CH0IMAE CH0OM[3]

CH0OM[2_0] : CH0OM[2:0]
bits : 0 - 2 (3 bit)
access : read-write

CH0PRE : CH0PRE
bits : 4 - 8 (5 bit)
access : read-write

CH0IMAE : CH0IMAE
bits : 5 - 10 (6 bit)
access : read-write

CH0OM[3] : CH0OM[3]
bits : 8 - 16 (9 bit)
access : read-write


PWM_CH1OCFR

PWM_CH1OCFR
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CH1OCFR PWM_CH1OCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1OM[2_0] CH1PRE CH1IMAE CH1OM[3]

CH1OM[2_0] : CH1OM[2:0]
bits : 0 - 2 (3 bit)
access : read-write

CH1PRE : CH1PRE
bits : 4 - 8 (5 bit)
access : read-write

CH1IMAE : CH1IMAE
bits : 5 - 10 (6 bit)
access : read-write

CH1OM[3] : CH1OM[3]
bits : 8 - 16 (9 bit)
access : read-write


PWM_CH2OCFR

PWM_CH2OCFR
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CH2OCFR PWM_CH2OCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH2OM[2_0] CH2PRE CH2IMAE CH2OM3[3]

CH2OM[2_0] : CH2OM[2:0]
bits : 0 - 2 (3 bit)
access : read-write

CH2PRE : CH2PRE
bits : 4 - 8 (5 bit)
access : read-write

CH2IMAE : CH2IMAE
bits : 5 - 10 (6 bit)
access : read-write

CH2OM3[3] : CH2OM3[3]
bits : 8 - 16 (9 bit)
access : read-write


PWM_CH3OCFR

PWM_CH3OCFR
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CH3OCFR PWM_CH3OCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH3OM[2_0] CH3PRE CH3IMAE CH3OM3[3]

CH3OM[2_0] : CH3OM[2:0]
bits : 0 - 2 (3 bit)
access : read-write

CH3PRE : CH3PRE
bits : 4 - 8 (5 bit)
access : read-write

CH3IMAE : CH3IMAE
bits : 5 - 10 (6 bit)
access : read-write

CH3OM3[3] : CH3OM3[3]
bits : 8 - 16 (9 bit)
access : read-write


PWM_CHCTR

PWM_CHCTR
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CHCTR PWM_CHCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0E CH1E CH2E CH3E

CH0E : CH0E
bits : 0 - 0 (1 bit)
access : read-write

CH1E : CH1E
bits : 2 - 4 (3 bit)
access : read-write

CH2E : CH2E
bits : 4 - 8 (5 bit)
access : read-write

CH3E : CH3E
bits : 6 - 12 (7 bit)
access : read-write


PWM_CHPOLR

PWM_CHPOLR
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CHPOLR PWM_CHPOLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0P CH1P CH2P CH3P

CH0P : CH0P
bits : 0 - 0 (1 bit)
access : read-write

CH1P : CH1P
bits : 2 - 4 (3 bit)
access : read-write

CH2P : CH2P
bits : 4 - 8 (5 bit)
access : read-write

CH3P : CH3P
bits : 6 - 12 (7 bit)
access : read-write


PWM_DICTR

PWM_DICTR
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_DICTR PWM_DICTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0CIE CH1CIE CH2CIE CH3CIE UEVIE TEVIE CH0CDE CH1CDE CH2CDE CH3CDE UEVDE TEVDE

CH0CIE : CH0CIE
bits : 0 - 0 (1 bit)
access : read-write

CH1CIE : CH1CIE
bits : 1 - 2 (2 bit)
access : read-write

CH2CIE : CH2CIE
bits : 2 - 4 (3 bit)
access : read-write

CH3CIE : CH3CIE
bits : 3 - 6 (4 bit)
access : read-write

UEVIE : UEVIE
bits : 8 - 16 (9 bit)
access : read-write

TEVIE : TEVIE
bits : 10 - 20 (11 bit)
access : read-write

CH0CDE : CH0CDE
bits : 16 - 32 (17 bit)
access : read-write

CH1CDE : CH1CDE
bits : 17 - 34 (18 bit)
access : read-write

CH2CDE : CH2CDE
bits : 18 - 36 (19 bit)
access : read-write

CH3CDE : CH3CDE
bits : 19 - 38 (20 bit)
access : read-write

UEVDE : UEVDE
bits : 24 - 48 (25 bit)
access : read-write

TEVDE : TEVDE
bits : 26 - 52 (27 bit)
access : read-write


PWM_EVGR

PWM_EVGR
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_EVGR PWM_EVGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0CG CH1CG CH2CG CH3CG UEVG TEVG

CH0CG : CH0CG
bits : 0 - 0 (1 bit)
access : read-write

CH1CG : CH1CG
bits : 1 - 2 (2 bit)
access : read-write

CH2CG : CH2CG
bits : 2 - 4 (3 bit)
access : read-write

CH3CG : CH3CG
bits : 3 - 6 (4 bit)
access : read-write

UEVG : UEVG
bits : 8 - 16 (9 bit)
access : read-write

TEVG : TEVG
bits : 10 - 20 (11 bit)
access : read-write


PWM_INTSR

PWM_INTSR
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_INTSR PWM_INTSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0CIF CH1CIF CH2CIF CH3CIF UEVIF TEVIF

CH0CIF : CH0CIF
bits : 0 - 0 (1 bit)
access : read-write

CH1CIF : CH1CIF
bits : 1 - 2 (2 bit)
access : read-write

CH2CIF : CH2CIF
bits : 2 - 4 (3 bit)
access : read-write

CH3CIF : CH3CIF
bits : 3 - 6 (4 bit)
access : read-write

UEVIF : UEVIF
bits : 8 - 16 (9 bit)
access : read-write

TEVIF : TEVIF
bits : 10 - 20 (11 bit)
access : read-write


PWM_TRCFR

PWM_TRCFR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_TRCFR PWM_TRCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRSEL

TRSEL : TRSEL
bits : 0 - 3 (4 bit)
access : read-write


PWM_CNTR

PWM_CNTR
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CNTR PWM_CNTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTV

CNTV : CNTV
bits : 0 - 15 (16 bit)
access : read-write


PWM_PSCR

PWM_PSCR
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_PSCR PWM_PSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSCV

PSCV : PSCV
bits : 0 - 15 (16 bit)
access : read-write


PWM_CRR

PWM_CRR
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CRR PWM_CRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRV

CRV : CRV
bits : 0 - 15 (16 bit)
access : read-write


PWM_CH0CR

PWM_CH0CR
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CH0CR PWM_CH0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0CV

CH0CV : CH0CV
bits : 0 - 15 (16 bit)
access : read-write


PWM_CH1CR (PWM_CH1CCR)

PWM_CH1CC
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CH1CR PWM_CH1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1CV

CH1CV : CH1CV
bits : 0 - 15 (16 bit)
access : read-write


PWM_CH2CR

PWM_CH2CR
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CH2CR PWM_CH2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH2CV

CH2CV : CH2CV
bits : 0 - 15 (16 bit)
access : read-write


PWM_CH3CR

PWM_CH3CR
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CH3CR PWM_CH3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH3CV

CH3CV : CH3CV
bits : 0 - 15 (16 bit)
access : read-write


PWM_CH0ACR

PWM_CH0ACR
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CH0ACR PWM_CH0ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0ACV

CH0ACV : CH0ACV
bits : 0 - 15 (16 bit)
access : read-write


PWM_CH1ACR

PWM_CH1ACR
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CH1ACR PWM_CH1ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1ACV

CH1ACV : CH1ACV
bits : 0 - 15 (16 bit)
access : read-write


PWM_CH2ACR

PWM_CH2ACR
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CH2ACR PWM_CH2ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH2ACV

CH2ACV : CH2ACV
bits : 0 - 15 (16 bit)
access : read-write


PWM_CH3ACR

PWM_CH3ACR
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CH3ACR PWM_CH3ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH3ACV

CH3ACV : CH3ACV
bits : 0 - 15 (16 bit)
access : read-write



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