\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
SCTM_CNTCFR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UEVDIS : UEVDIS
bits : 0 - 0 (1 bit)
access : read-write
UGDIS : UGDIS
bits : 1 - 2 (2 bit)
access : read-write
CKDIV : CKDIV
bits : 8 - 17 (10 bit)
access : read-write
SCTM_CTR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TME : TME
bits : 0 - 0 (1 bit)
access : read-write
CRBE : CRBE
bits : 1 - 2 (2 bit)
access : read-write
SCTM_CH0ICFR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TI0F : TI0F
bits : 0 - 3 (4 bit)
access : read-write
CH0CCS : CH0CCS
bits : 16 - 33 (18 bit)
access : read-write
CH0PSC : CH0PSC
bits : 18 - 37 (20 bit)
access : read-write
SCTM_MDCFR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMSEL : SMSEL
bits : 8 - 18 (11 bit)
access : read-write
SCTM_CH0OCFR
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0OM : CH0OM
bits : 0 - 2 (3 bit)
access : read-write
CH0PRE : CH0PRE
bits : 4 - 8 (5 bit)
access : read-write
SCTM_CHCTR
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0E : CH0E
bits : 0 - 0 (1 bit)
access : read-write
SCTM_CHPOLR
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0P : CH0P
bits : 0 - 0 (1 bit)
access : read-write
SCTM_DICTR
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0CCIE : CH0CCIE
bits : 0 - 0 (1 bit)
access : read-write
UEVIE : UEVIE
bits : 8 - 16 (9 bit)
access : read-write
TEVIE : TEVIE
bits : 10 - 20 (11 bit)
access : read-write
SCTM_EVGR
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0CCG : CH0CCG
bits : 0 - 0 (1 bit)
access : read-write
UEVG : UEVG
bits : 8 - 16 (9 bit)
access : read-write
TEVG : TEVG
bits : 10 - 20 (11 bit)
access : read-write
SCTM_INTSR
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0CCIF : CH0CCIF
bits : 0 - 0 (1 bit)
access : read-write
CH0OCF : CH0OCF
bits : 4 - 8 (5 bit)
access : read-write
UEVIF : UEVIF
bits : 8 - 16 (9 bit)
access : read-write
TEVIF : TEVIF
bits : 10 - 20 (11 bit)
access : read-write
SCTM_TRCFR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRSEL : TRSEL
bits : 0 - 3 (4 bit)
access : read-write
SCTM_CNTR
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTV : CNTV
bits : 0 - 15 (16 bit)
access : read-write
SCTM_PSCR
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSCV : PSCV
bits : 0 - 15 (16 bit)
access : read-write
SCTM_CRR
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRV : CRV
bits : 0 - 15 (16 bit)
access : read-write
SCTM_CH0CCR
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0CCV : CH0CCV
bits : 0 - 15 (16 bit)
access : read-write
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