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SCTM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

SCTM_CNTCFR

SCTM_CTR

SCTM_CH0ICFR

SCTM_MDCFR

SCTM_CH0OCFR

SCTM_CHCTR

SCTM_CHPOLR

SCTM_DICTR

SCTM_EVGR

SCTM_INTSR

SCTM_TRCFR

SCTM_CNTR

SCTM_PSCR

SCTM_CRR

SCTM_CH0CCR


SCTM_CNTCFR

SCTM_CNTCFR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTM_CNTCFR SCTM_CNTCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEVDIS UGDIS CKDIV

UEVDIS : UEVDIS
bits : 0 - 0 (1 bit)
access : read-write

UGDIS : UGDIS
bits : 1 - 2 (2 bit)
access : read-write

CKDIV : CKDIV
bits : 8 - 17 (10 bit)
access : read-write


SCTM_CTR

SCTM_CTR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTM_CTR SCTM_CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TME CRBE

TME : TME
bits : 0 - 0 (1 bit)
access : read-write

CRBE : CRBE
bits : 1 - 2 (2 bit)
access : read-write


SCTM_CH0ICFR

SCTM_CH0ICFR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTM_CH0ICFR SCTM_CH0ICFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TI0F CH0CCS CH0PSC

TI0F : TI0F
bits : 0 - 3 (4 bit)
access : read-write

CH0CCS : CH0CCS
bits : 16 - 33 (18 bit)
access : read-write

CH0PSC : CH0PSC
bits : 18 - 37 (20 bit)
access : read-write


SCTM_MDCFR

SCTM_MDCFR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTM_MDCFR SCTM_MDCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMSEL

SMSEL : SMSEL
bits : 8 - 18 (11 bit)
access : read-write


SCTM_CH0OCFR

SCTM_CH0OCFR
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTM_CH0OCFR SCTM_CH0OCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0OM CH0PRE

CH0OM : CH0OM
bits : 0 - 2 (3 bit)
access : read-write

CH0PRE : CH0PRE
bits : 4 - 8 (5 bit)
access : read-write


SCTM_CHCTR

SCTM_CHCTR
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTM_CHCTR SCTM_CHCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0E

CH0E : CH0E
bits : 0 - 0 (1 bit)
access : read-write


SCTM_CHPOLR

SCTM_CHPOLR
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTM_CHPOLR SCTM_CHPOLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0P

CH0P : CH0P
bits : 0 - 0 (1 bit)
access : read-write


SCTM_DICTR

SCTM_DICTR
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTM_DICTR SCTM_DICTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0CCIE UEVIE TEVIE

CH0CCIE : CH0CCIE
bits : 0 - 0 (1 bit)
access : read-write

UEVIE : UEVIE
bits : 8 - 16 (9 bit)
access : read-write

TEVIE : TEVIE
bits : 10 - 20 (11 bit)
access : read-write


SCTM_EVGR

SCTM_EVGR
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTM_EVGR SCTM_EVGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0CCG UEVG TEVG

CH0CCG : CH0CCG
bits : 0 - 0 (1 bit)
access : read-write

UEVG : UEVG
bits : 8 - 16 (9 bit)
access : read-write

TEVG : TEVG
bits : 10 - 20 (11 bit)
access : read-write


SCTM_INTSR

SCTM_INTSR
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTM_INTSR SCTM_INTSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0CCIF CH0OCF UEVIF TEVIF

CH0CCIF : CH0CCIF
bits : 0 - 0 (1 bit)
access : read-write

CH0OCF : CH0OCF
bits : 4 - 8 (5 bit)
access : read-write

UEVIF : UEVIF
bits : 8 - 16 (9 bit)
access : read-write

TEVIF : TEVIF
bits : 10 - 20 (11 bit)
access : read-write


SCTM_TRCFR

SCTM_TRCFR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTM_TRCFR SCTM_TRCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRSEL

TRSEL : TRSEL
bits : 0 - 3 (4 bit)
access : read-write


SCTM_CNTR

SCTM_CNTR
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTM_CNTR SCTM_CNTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTV

CNTV : CNTV
bits : 0 - 15 (16 bit)
access : read-write


SCTM_PSCR

SCTM_PSCR
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTM_PSCR SCTM_PSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSCV

PSCV : PSCV
bits : 0 - 15 (16 bit)
access : read-write


SCTM_CRR

SCTM_CRR
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTM_CRR SCTM_CRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRV

CRV : CRV
bits : 0 - 15 (16 bit)
access : read-write


SCTM_CH0CCR

SCTM_CH0CCR
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTM_CH0CCR SCTM_CH0CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0CCV

CH0CCV : CH0CCV
bits : 0 - 15 (16 bit)
access : read-write



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