\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
LCD_LCDCR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDEN : LCDEN
bits : 0 - 0 (1 bit)
access : read-write
LCDPR : LCDPR
bits : 1 - 2 (2 bit)
access : read-write
DTYC : DTYC
bits : 2 - 6 (5 bit)
access : read-write
BIAS : BIAS
bits : 5 - 11 (7 bit)
access : read-write
TYPE : TYPE
bits : 7 - 14 (8 bit)
access : read-write
MUXCOM4 : MUXCOM4
bits : 8 - 16 (9 bit)
access : read-write
MUXCOM5 : MUXCOM5
bits : 9 - 18 (10 bit)
access : read-write
MUXCOM6 : MUXCOM6
bits : 10 - 20 (11 bit)
access : read-write
MUXCOM7 : MUXCOM7
bits : 11 - 22 (12 bit)
access : read-write
DSTAO : DSTAO
bits : 14 - 28 (15 bit)
access : read-write
HRLEN : HRLEN
bits : 15 - 30 (16 bit)
access : read-write
MMASK : MMASK
bits : 24 - 48 (25 bit)
access : read-write
LCD_LCDSCR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFC : SOFC
bits : 0 - 0 (1 bit)
access : read-write
UDDC : UDDC
bits : 1 - 2 (2 bit)
access : read-write
LCD_LCDRAM0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG_DATA : SEG_DATA
bits : 0 - 31 (32 bit)
access : read-write
LCD_LCDRAM1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG_DATA : SEG_DATA
bits : 0 - 31 (32 bit)
access : read-write
LCD_LCDRAM2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG_DATA : SEG_DATA
bits : 0 - 31 (32 bit)
access : read-write
LCD_LCDRAM3
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG_DATA : SEG_DATA
bits : 0 - 31 (32 bit)
access : read-write
LCD_LCDRAM4
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG_DATA : SEG_DATA
bits : 0 - 31 (32 bit)
access : read-write
LCD_LCDRAM5
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG_DATA : SEG_DATA
bits : 0 - 31 (32 bit)
access : read-write
LCD_LCDRAM6
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG_DATA : SEG_DATA
bits : 0 - 31 (32 bit)
access : read-write
LCD_LCDRAM7
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG_DATA : SEG_DATA
bits : 0 - 31 (32 bit)
access : read-write
LCD_LCDFCR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HDEN : HDEN
bits : 0 - 0 (1 bit)
access : read-write
HDD : HDD
bits : 4 - 10 (7 bit)
access : read-write
DEAD : DEAD
bits : 7 - 16 (10 bit)
access : read-write
CPVS : CPVS
bits : 10 - 22 (13 bit)
access : read-write
BLINKF : BLINKF
bits : 13 - 28 (16 bit)
access : read-write
BLINK : BLINK
bits : 16 - 33 (18 bit)
access : read-write
LCDDIV : LCDDIV
bits : 18 - 39 (22 bit)
access : read-write
LCDPS : LCDPS
bits : 22 - 47 (26 bit)
access : read-write
LCD_LCDRAM8
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG_DATA : SEG_DATA
bits : 0 - 31 (32 bit)
access : read-write
LCD_LCDRAM9
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG_DATA : SEG_DATA
bits : 0 - 31 (32 bit)
access : read-write
LCD_LCDRAM10
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG_DATA : SEG_DATA
bits : 0 - 31 (32 bit)
access : read-write
LCD_LCDRAM11
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG_DATA : SEG_DATA
bits : 0 - 31 (32 bit)
access : read-write
LCD_LCDRAM12
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG_DATA : SEG_DATA
bits : 0 - 31 (32 bit)
access : read-write
LCD_LCDRAM13
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG_DATA : SEG_DATA
bits : 0 - 31 (32 bit)
access : read-write
LCD_LCDRAM14
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG_DATA : SEG_DATA
bits : 0 - 31 (32 bit)
access : read-write
LCD_LCDRAM15
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG_DATA : SEG_DATA
bits : 0 - 31 (32 bit)
access : read-write
LCD_LCDIER
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFIE : SOFIE
bits : 0 - 0 (1 bit)
access : read-write
UDDIE : UDDIE
bits : 1 - 2 (2 bit)
access : read-write
LCD_LCDSR
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDENS : LCDENS
bits : 0 - 0 (1 bit)
access : read-write
SOF : SOF
bits : 1 - 2 (2 bit)
access : read-write
UDR : UDR
bits : 2 - 4 (3 bit)
access : read-write
UDD : UDD
bits : 3 - 6 (4 bit)
access : read-write
RDY : RDY
bits : 4 - 8 (5 bit)
access : read-write
FCRSF : FCRSF
bits : 5 - 10 (6 bit)
access : read-write
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