FMC_ISPCTL (ISPCTL)

FMC_ISPTRG (ISPTRG)

FMC_DFBA (DFBA)

FMC_FTCTL (FTCTL)

FMC_ISPADDR (ISPADDR)

FMC_ISPSTS (ISPSTS)

FMC_ISPDAT (ISPDAT)

FMC_ISPCMD (ISPCMD)

ISPEN : ISP Enable Bit (Write Protect) Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BS : Boot Selection (Write Protect) Set/clear this bit to select next booting from LDROM/APROM. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPUEN : SPROM Update Enable Bit (Write Protect) Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

APUEN : APROM Update Enable Bit (Write Protect) Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGUEN : CONFIG Update Enable Bit (Write Protect) Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDUEN : LDROM Update Enable Bit (Write Protect) LDROM update enable bit. Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect) This bit is set by hardware when user triggers ISPGO (FMC_ISPTRG[0]) and meets any of the following conditions: This bit needs to be cleared by writing 1 to it. Code is executed from APROM and tries to write APROM if APUEN is set to 0. Code is executed from LDROM and tries to write LDROM if LDUEN is set to 0. CONFIG is erased/programmed if CFGUEN is set to 0. SPROM is erased/programmed if SPUEN is set to 0. SPROM is programmed at SPROM secured mode. Page Erase command at LOCK mode with ICE connection. Erase or Program command at brown-out detected. Destination address is illegal, such as over an available range. Invalid ISP commands. Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

ISPGO : ISP Start Trigger (Write Protect) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFBA : Data Flash Base Address (Read Only) This register indicates Data Flash start address. The Data Flash is shared with APROM. The content of this register is loaded from CONFIG1.
bits : 0 - 31 (32 bit)
access : read-only

FOM : Frequency Optimization Mode (Write Protect) This chip supports adjustable Flash access timing to optimize the Flash access cycles in different system working frequency. For 32/64 Kbytes Flash: Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPADDR : ISP Address This chip is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. For CRC32 Checksum Calculation command, this field is the Flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation. 32/64 Kbytes Flash: ISPADR[8:0] must be kept all 0 for Vector Page Re-map Command.
bits : 0 - 31 (32 bit)
access : read-write

ISPBUSY : ISP BUSY (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CBS : Boot Selection of CONFIG (Read Only) This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect) This bit is set by hardware when user triggers ISPGO (FMC_ISPTRG[0]) and meets any of the following conditions: This bit needs to be cleared by writing 1 to it. Code is executed from APROM and tries to write APROM if APUEN is set to 0. Code is executed from LDROM and tries to write LDROM if LDUEN is set to 0. CONFIG is erased/programmed if CFGUEN is set to 0. SPROM is erased/programmed if SPUEN is set to 0. SPROM is programmed at SPROM secured mode. Page Erase command at LOCK mode with ICE connection. Erase or Program command at brown-out detected. Destination address is illegal, such as over an available range. Invalid ISP commands.
bits : 6 - 6 (1 bit)
access : read-write

VECMAP : Vector Page Mapping Address (Read Only) All access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}, except SPROM. VECMAP [18:12] should be 0.
bits : 9 - 29 (21 bit)
access : read-only

SCODE : Security Code Active Flag This bit is set to 1 by hardware when detecting SPROM secured code is active at Flash initialization, or software writes 1 to this bit to make secured code active this bit is only cleared by SPROM page erase operation.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPDAT : ISP Data Write data to this register before ISP program operation. Read data from this register after ISP read operation.
bits : 0 - 31 (32 bit)
access : read-write

CMD : ISP CMD ISP command table is shown below: The other commands are invalid.
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.