\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x20 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x50 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x90 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xB0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xD4 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xE0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xE8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xF8 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x110 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x120 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x200 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x250 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x304 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x31C Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :
BPWM Control Register 0
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRLDn : Center Re-Load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
bits : 0 - 5 (6 bit)
access : read-write
IMMLDENn : Immediately Load Enable
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
1 : 1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
End of enumeration elements list.
DBGHALT : ICE Debug Mode Counter Halt (Write Protect)
If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode.
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode counter halt disable
#1 : 1
ICE debug mode counter halt enable
End of enumeration elements list.
DBGTRIOFF : ICE Debug Mode Acknowledge Disable (Write Protect)
BPWM pin will keep output no matter ICE debug mode acknowledged or not.
Note: This register is write protected. Refer to SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement effects BPWM output
#1 : 1
ICE debug mode acknowledgement disabled
End of enumeration elements list.
BPWM Clock Source Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECLKSRC0 : BPWM_CH01 External Clock Source Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
BPWMx_CLK, x denotes 0 or 1
#001 : 1
TIMER0 overflow
#010 : 2
TIMER1 overflow
#011 : 3
TIMER2 overflow
#100 : 4
TIMER3 overflow
End of enumeration elements list.
BPWM Synchronous Start Control Register
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSEN0 : BPWM Synchronous Start Function Enable 0
When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM synchronous start function Disabled
#1 : 1
BPWM synchronous start function Enabled
End of enumeration elements list.
SSRC : BPWM Synchronous Start Source Select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Synchronous start source come from BPWM0
#01 : 1
Synchronous start source come from BPWM1
#10 : 2
Synchronous start source come from BPWM0
#11 : 3
Synchronous start source come from BPWM1
End of enumeration elements list.
BPWM Synchronous Start Trigger Register
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CNTSEN : BPWM Counter Synchronous Start Enable (Write Only)
PMW counter synchronous enable function is used to make selected BPWM channels (include BPWM0_CHx and BPWM1_CHx) start counting at the same time.
Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated BPWM channel counter synchronous start function is enabled.
Note: This bit only present in BPWM0_BA.
bits : 0 - 0 (1 bit)
access : write-only
BPWM Status Register
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTMAX0 : Time-Base Counter 0 Equal To 0xFFFF Latched Status
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates the time-base counter never reached its maximum value 0xFFFF
#1 : 1
Indicates the time-base counter reached its maximum value, software can write 1 to clear this bit
End of enumeration elements list.
ADCTRGn : ADC Start Of Conversion Status
Each bit n controls the corresponding BPWM channel n.
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : 0
Indicates no ADC start of conversion trigger event has occurred
1 : 1
Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
BPWM Clock Pre-scale Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKPSC : BPWM Counter Clock Pre-Scale
The clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1).
bits : 0 - 11 (12 bit)
access : read-write
BPWM Counter Enable Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTEN0 : BPWM Counter Enable 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Counter and clock prescaler Stop Running
#1 : 1
BPWM Counter and clock prescaler Start Running
End of enumeration elements list.
BPWM Capture Input Enable Register
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPINENn : Capture Input Enable Control
Each bit n controls the corresponding BPWM channel n.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
1 : 1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
BPWM Capture Control Register
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPENn : Capture Function Enable Control
Each bit n controls the corresponding BPWM channel n.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
1 : 1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPINVn : Capture Inverter Enable Control
Each bit n controls the corresponding BPWM channel n.
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0 : 0
Capture source inverter Disabled
1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
RCRLDENn : Rising Capture Reload Enable Control
Each bit n controls the corresponding BPWM channel n.
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : 0
Rising capture reload counter Disabled
1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
FCRLDENn : Falling Capture Reload Enable Control
Each bit n controls the corresponding BPWM channel n.
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0 : 0
Falling capture reload counter Disabled
1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
BPWM Capture Status Register
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRLIFOVn : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
bits : 0 - 5 (6 bit)
access : read-only
CFLIFOVn : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
bits : 8 - 13 (6 bit)
access : read-only
BPWM Rising Capture Data Register 0
address_offset : 0x20C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RCAPDAT : BPWM Rising Capture Data Register (Read Only)
When rising capture condition happened, the BPWM counter value will be saved in this register.
bits : 0 - 15 (16 bit)
access : read-only
BPWM Falling Capture Data Register 0
address_offset : 0x210 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FCAPDAT : BPWM Falling Capture Data Register (Read Only)
When falling capture condition happened, the BPWM counter value will be saved in this register.
bits : 0 - 15 (16 bit)
access : read-only
BPWM Rising Capture Data Register 1
address_offset : 0x214 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Falling Capture Data Register 1
address_offset : 0x218 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Rising Capture Data Register 2
address_offset : 0x21C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Falling Capture Data Register 2
address_offset : 0x220 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Rising Capture Data Register 3
address_offset : 0x224 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Falling Capture Data Register 3
address_offset : 0x228 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Rising Capture Data Register 4
address_offset : 0x22C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Falling Capture Data Register 4
address_offset : 0x230 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Rising Capture Data Register 5
address_offset : 0x234 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Falling Capture Data Register 5
address_offset : 0x238 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Clear Counter Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTCLR0 : Clear BPWM Counter Control Bit 0
It is automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit BPWM counter to 0000H
End of enumeration elements list.
BPWM Capture Interrupt Enable Register
address_offset : 0x250 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPRIENn : BPWM Capture Rising Latch Interrupt Enable Control
Each bit n controls the corresponding BPWM channel n.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Capture rising edge latch interrupt Disabled
1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPFIENn : BPWM Capture Falling Latch Interrupt Enable Control
Each bit n controls the corresponding BPWM channel n.
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0 : 0
Capture falling edge latch interrupt Disabled
1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
BPWM Capture Interrupt Flag Register
address_offset : 0x254 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRLIFn : BPWM Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
No capture rising latch condition happened
1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIFn : BPWM Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0 : 0
No capture falling latch condition happened
1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
BPWM Period Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : BPWM Period Register
Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.
Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
bits : 0 - 15 (16 bit)
access : read-write
BPWM PERIOD Buffer
address_offset : 0x304 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PBUF : BPWM Period Register Buffer (Read Only)
Used as PERIOD active register.
bits : 0 - 15 (16 bit)
access : read-only
BPWM CMPDAT0 Buffer
address_offset : 0x31C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMPBUF : BPWM Comparator Register Buffer (Read Only)
Used as CMP active register.
bits : 0 - 15 (16 bit)
access : read-only
BPWM CMPDAT1 Buffer
address_offset : 0x320 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM CMPDAT2 Buffer
address_offset : 0x324 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM CMPDAT3 Buffer
address_offset : 0x328 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM CMPDAT4 Buffer
address_offset : 0x32C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM CMPDAT5 Buffer
address_offset : 0x330 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Control Register 1
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTTYPE0 : BPWM Counter Behavior Type 0
Each bit n controls corresponding BPWM channel n.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supports in capture mode)
#01 : 1
Down count type (supports in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved.
End of enumeration elements list.
BPWM Comparator Register 0
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : BPWM Comparator Register
CMP use to compare with CNT to generate BPWM waveform, interrupt and trigger ADC.
In independent mode, BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.
In complementary mode, BPWM_CMPDAT0, 2, 4 denote as first compared point, and BPWM_CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs BPWM_CH0 and BPWM_CH1, BPWM_CH2 and BPWM_CH3, BPWM_CH4 and BPWM_CH5.
bits : 0 - 15 (16 bit)
access : read-write
BPWM Comparator Register 1
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Comparator Register 2
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Comparator Register 3
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Comparator Register 4
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Comparator Register 5
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Counter Register 0
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : BPWM Data Register (Read Only)
User can monitor CNT to know the current value in 16-bit period counter.
bits : 0 - 15 (16 bit)
access : read-only
DIRF : BPWM Direction Indicator Flag (Read Only)
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Counter is Down count
#1 : 1
Counter is UP count
End of enumeration elements list.
BPWM Generation Register 0
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZPCTLn : BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to zero.
bits : 0 - 11 (12 bit)
access : read-write
Enumeration:
00 : 0
Do nothing
01 : 1
BPWM zero point output Low
10 : 10
BPWM zero point output High
11 : 11
BPWM zero point output Toggle
End of enumeration elements list.
PRDPCTLn : BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIODn+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
bits : 16 - 27 (12 bit)
access : read-write
Enumeration:
00 : 0
Do nothing
01 : 1
BPWM period (center) point output Low
10 : 10
BPWM period (center) point output High
11 : 11
BPWM period (center) point output Toggle
End of enumeration elements list.
BPWM Generation Register 1
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPUCTLn : BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
bits : 0 - 11 (12 bit)
access : read-write
Enumeration:
00 : 0
Do nothing
01 : 1
BPWM compare up point output Low
10 : 10
BPWM compare up point output High
11 : 11
BPWM compare up point output Toggle
End of enumeration elements list.
CMPDCTLn : BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
bits : 16 - 27 (12 bit)
access : read-write
Enumeration:
00 : 0
Do nothing
01 : 1
BPWM compare down point output Low
10 : 10
BPWM compare down point output High
11 : 11
BPWM compare down point output Toggle
End of enumeration elements list.
BPWM Mask Enable Register
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKENn : BPWM Mask Enable Control
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
BPWM output signal is non-masked
1 : 1
BPWM output signal is masked and output MSKDATn data
End of enumeration elements list.
BPWM Mask Data Register
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKDATn : BPWM Mask Data Bit
This data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Output logic low to BPWMn
1 : 1
Output logic high to BPWMn
End of enumeration elements list.
BPWM Pin Polar Inverse Register
address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PINVn : BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
BPWM output polar inverse Disabled
1 : 1
BPWM output polar inverse Enabled
End of enumeration elements list.
BPWM Output Enable Register
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POENn : BPWM Pin Output Enable Control
Each bit n controls the corresponding BPWM channel n.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
BPWM pin at tri-state
1 : 1
BPWM pin in output mode
End of enumeration elements list.
BPWM Interrupt Enable Register
address_offset : 0xE0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZIEN0 : BPWM Zero Point Interrupt Enable 0
Note: Odd channels will read always 0 at complementary mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
PIEN0 : BPWM Period Point Interrupt Enable 0
Note: When up-down counter type period point means center point.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
CMPUIENn : BPWM Compare Up Count Interrupt Enable Control
Each bit n controls the corresponding BPWM channel n.
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : 0
Compare up count interrupt Disabled
1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPDIENn : BPWM Compare Down Count Interrupt Enable Control
Each bit n controls the corresponding BPWM channel n.
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0 : 0
Compare down count interrupt Disabled
1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
BPWM Interrupt Flag Register
address_offset : 0xE8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZIF0 : BPWM Zero Point Interrupt Flag 0
This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero.
bits : 0 - 0 (1 bit)
access : read-write
PIF0 : BPWM Period Point Interrupt Flag 0
This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero.
bits : 8 - 8 (1 bit)
access : read-write
CMPUIFn : BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
bits : 16 - 21 (6 bit)
access : read-write
CMPDIFn : BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
bits : 24 - 29 (6 bit)
access : read-write
BPWM Trigger ADC Source Select Register 0
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL0 : BPWM_CH0 Trigger ADC Source Select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
BPWM_CH0 zero point
#0001 : 1
BPWM_CH0 period point
#0010 : 2
BPWM_CH0 zero or period point
#0011 : 3
BPWM_CH0 up-count CMPDAT point
#0100 : 4
BPWM_CH0 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
BPWM_CH1 up-count CMPDAT point
#1001 : 9
BPWM_CH1 down-count CMPDAT point
End of enumeration elements list.
TRGEN0 : BPWM_CH0 Trigger ADC Enable Control
bits : 7 - 7 (1 bit)
access : read-write
TRGSEL1 : BPWM_CH1 Trigger ADC Source Select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
BPWM_CH0 zero point
#0001 : 1
BPWM_CH0 period point
#0010 : 2
BPWM_CH0 zero or period point
#0011 : 3
BPWM_CH0 up-count CMPDAT point
#0100 : 4
BPWM_CH0 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
BPWM_CH1 up-count CMPDAT point
#1001 : 9
BPWM_CH1 down-count CMPDAT point
End of enumeration elements list.
TRGEN1 : BPWM_CH1 Trigger ADC Enable Control
bits : 15 - 15 (1 bit)
access : read-write
TRGSEL2 : BPWM_CH2 Trigger ADC Source Select
Others reserved.
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
BPWM_CH2 zero point
#0001 : 1
BPWM_CH2 period point
#0010 : 2
BPWM_CH2 zero or period point
#0011 : 3
BPWM_CH2 up-count CMPDAT point
#0100 : 4
BPWM_CH2 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
BPWM_CH3 up-count CMPDAT point
#1001 : 9
BPWM_CH3 down-count CMPDAT point
End of enumeration elements list.
TRGEN2 : BPWM_CH2 Trigger ADC Enable Control
bits : 23 - 23 (1 bit)
access : read-write
TRGSEL3 : BPWM_CH3 Trigger ADC Source Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
BPWM_CH2 zero point
#0001 : 1
BPWM_CH2 period point
#0010 : 2
BPWM_CH2 zero or period point
#0011 : 3
BPWM_CH2 up-count CMPDAT point
#0100 : 4
BPWM_CH2 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
BPWM_CH3 up-count CMPDAT point
#1001 : 9
BPWM_CH3 down-count CMPDAT point
End of enumeration elements list.
TRGEN3 : BPWM_CH3 Trigger ADC Enable Control
bits : 31 - 31 (1 bit)
access : read-write
BPWM Trigger ADC Source Select Register 1
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL4 : BPWM_CH4 Trigger ADC Source Select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
BPWM_CH4 zero point
#0001 : 1
BPWM_CH4 period point
#0010 : 2
BPWM_CH4 zero or period point
#0011 : 3
BPWM_CH4 up-count CMPDAT point
#0100 : 4
BPWM_CH4 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
BPWM_CH5 up-count CMPDAT point
#1001 : 9
BPWM_CH5 down-count CMPDAT point
End of enumeration elements list.
TRGEN4 : BPWM_CH4 Trigger ADC Enable Control
bits : 7 - 7 (1 bit)
access : read-write
TRGSEL5 : BPWM_CH5 Trigger ADC Source Select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
BPWM_CH4 zero point
#0001 : 1
BPWM_CH4 period point
#0010 : 2
BPWM_CH4 zero or period point
#0011 : 3
BPWM_CH4 up-count CMPDAT point
#0100 : 4
BPWM_CH4 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
BPWM_CH5 up-count CMPDAT point
#1001 : 9
BPWM_CH5 down-count CMPDAT point
End of enumeration elements list.
TRGEN5 : BPWM_CH5 Trigger ADC Enable Control
bits : 15 - 15 (1 bit)
access : read-write
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