\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
CRC Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRCEN : CRC Generator Enable Bit
Set this bit 1 to enable CRC generator for CRC operation.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
CRC generator is active
End of enumeration elements list.
CHKSINIT : Checksum Initialization
Set this bit will auto reolad SEED (CRC_SEED [31:0]) to CHECKSUM (CRC_CHECKSUM[31:0]) as CRC operation initial value.
Note: This bit will be cleared automatically.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reolad SEED value to CHECKSUM as CRC operation initial value
End of enumeration elements list.
DATREV : Write Data Bit Order Reverse Enable Bit
This bit is used to enable the bit order reverse function per byte for write data value DATA (CRC_DATA[31:0]).
Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit order reversed for CRC DATA Disabled
#1 : 1
Bit order reversed for CRC DATA Enabled (per byte)
End of enumeration elements list.
CHKSREV : Checksum Bit Order Reverse Enable Bit
This bit is used to enable the bit order reverse function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]).
Note: If the checksum result is 0xDD7B0F2E, the bit order reverse result for CRC checksum is 0x74F0DEBB.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit order reverse for CRC CHECKSUM Disabled
#1 : 1
Bit order reverse for CRC CHECKSUM Enabled
End of enumeration elements list.
DATFMT : Write Data 1's Complement Enable Bit
This bit is used to enable the 1's complement function for write data value DATA (CRC_DATA[31:0]).
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
1's complement for CRC DATA Disabled
#1 : 1
1's complement for CRC DATA Enabled
End of enumeration elements list.
CHKSFMT : Checksum 1's Complement Enable Bit
This bit is used to enable the 1's complement function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]).
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
1's complement for CRC CHECKSUM Disabled
#1 : 1
1's complement for CRC CHECKSUM Enabled
End of enumeration elements list.
DATLEN : CPU Write Data Length
This field indicates the valid write data length of DATA (CRC_DAT[31:0]).
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Data length is 8-bit mode
#01 : 1
Data length is 16-bit mode.
Data length is 32-bit mode
End of enumeration elements list.
CRCMODE : CRC Polynomial Mode
This field indicates the CRC operation polynomial mode.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
CRC-CCITT Polynomial mode
#01 : 1
CRC-8 Polynomial mode
#10 : 2
CRC-16 Polynomial mode
#11 : 3
CRC-32 Polynomial mode
End of enumeration elements list.
CRC Write Data Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : CRC Write Data Bits
User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
bits : 0 - 31 (32 bit)
access : read-write
CRC Seed Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEED : CRC Seed Value
This field indicates the CRC seed value.
Note1: This SEED value will be loaded to checksum initial value CHECKSUM (CRC_CHECKSUM[31:0]) after set CHKSINIT (CRC_CTL[1]) to 1.
Note2: The valid bits of CRC_SEED[31:0] is correlated to CRCMODE (CRC_CTL[31:30]).
bits : 0 - 31 (32 bit)
access : read-write
CRC Checksum Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHECKSUM : CRC Checksum Results
This field indicates the CRC checksum result.
Note: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30]).
bits : 0 - 31 (32 bit)
access : read-only
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