\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
ISP Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPEN : ISP Enable Bit (Write Protect )
ISP function enable bit. Set this bit to enable ISP function.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP function Disabled
#1 : 1
ISP function Enabled
End of enumeration elements list.
BS : Boot Select (Write Protect )
Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Boot from APROM
#1 : 1
Boot from LDROM
End of enumeration elements list.
APUEN : APROM Update Enable Bit (Write Protect)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
APROM cannot be updated when chip runs in APROM
#1 : 1
APROM can be updated when chip runs in APROM
End of enumeration elements list.
CFGUEN : Enable Config Update By ISP (Write Protect)
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP update config-bit Disabled
#1 : 1
ISP update config-bit Enabled
End of enumeration elements list.
LDUEN : LDROM Update Enable Bit (Write Protect)
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
LDROM cannot be updated
#1 : 1
LDROM can be updated when chip runs in APROM
End of enumeration elements list.
ISPFF : ISP Fail Flag (Write Protect)
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself if APUEN is set to 0
(2) LDROM writes to itself if LDUEN is set to 0
(3) CONFIG is erased/programmed if CFGUEN is set to 0
(4) Destination address is illegal, such as over an available range
Write 1 to clear to this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write
ISP Trigger Control Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPGO : ISP Start Trigger (Write-Protection Bit)
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
This bit is the protected bit, It means programming this bit needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP operation finished
#1 : 1
ISP progressed
End of enumeration elements list.
Data Flash Base Address
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DFBADR : Data Flash Base Address
This register indicates Data Flash start address. It is read only.
Tthe Data Flash size is defined by user configuration, register content is loaded from CONFIG1 when chip is powered on.
bits : 0 - 31 (32 bit)
access : read-only
Flash Access Time Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FOMSEL0 : Chip Frequency Optimization Mode Select 0 (Write-Protection Bit)
When CPU frequency is lower than 72 MHz, user can modify flash access delay cycle by FOMSEL1 and FOMSEL0 to improve system performance.
bits : 4 - 4 (1 bit)
access : read-write
FOMSEL1 : Chip Frequency Optimization Mode Select1 (Write-protection Bit)
bits : 6 - 6 (1 bit)
access : read-write
ISP Address Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPADR : ISP Address
The NuMicro M071R_S series has a maximum of 32Kx32 (128 KB) embedded Flash, which supports word program only. ISPADR[1:0] must be kept 00b for ISP operation.
bits : 0 - 31 (32 bit)
access : read-write
ISP Status Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPGO : ISP Start Trigger (Read Only)
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
Note: This bit is the same as ISPTRG bit0
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
ISP operation finished
#1 : 1
ISP operation progressed
End of enumeration elements list.
CBS : Chip Boot Selection (Read Only)
This is a mirror of CBS in CONFIG0.
bits : 1 - 2 (2 bit)
access : read-only
ISPFF : ISP Fail Flag (Write-Protection Bit)
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself
(2) LDROM writes to itself
(3) CONFIG is erased/programmed if CFGUEN is set to 0
(4) Destination address is illegal, such as over an available range
Write 1 to clear this bit.
Note: The function of this bit is the same as ISPCON bit6
bits : 6 - 6 (1 bit)
access : read-write
VECMAP : Vector Page Mapping Address (Read Only)
The current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}
bits : 9 - 20 (12 bit)
access : read-only
ISP Data Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT : ISP Data
Write data to this register before ISP program operation
Read data from this register after ISP read operation
bits : 0 - 31 (32 bit)
access : read-write
ISP Command Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPCMD : ISP Command
ISP command table is shown below:
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00 : 0
Read
0x04 : 4
Read Unique ID
0x0b : 11
Read Company ID (0xDA)
0x21 : 33
Program
0x22 : 34
Page Erase
0x2e : 46
Set Vector Page Re-Map
End of enumeration elements list.
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