ADDR0

ADDR4

ADDR5

ADDR6

ADDR7

ADCR

ADCHER

ADCMPR0

ADCMPR1

ADSR

ADDR1

ADPDMA

ADDR8

ADDR9

ADDR10

ADDR11

ADDR2

ADDR3

RSLT : A/D Conversion Result This field contains conversion result of ADC.
bits : 0 - 15 (16 bit)
access : read-only

OVERRUN : Overrun Flag If converted data in RSLT has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read. This is a read only bit.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

VALID : Valid Flag This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read. This is a read only bit
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ADEN : A/D Converter Enable Bit Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADIE : A/D Interrupt Enable Bit A/D conversion end interrupt request is generated if ADIE bit (ADCR[1]) is set to 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMD : A/D Converter Operation Mode When changing the operation mode, software should disable ADST bit (ADCR[11]) firstly.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGS : Hardware Trigger Source Software should disable TRGEN (ADCR[8]) and ADST (ADCR[11]) before change TRGS.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGCOND : External Trigger Condition These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGEN : Hardware Trigger Enable Bit Enable or disable triggering of A/D conversion by hardware (external STADC pin or PWM Center-aligned trigger). ADC hardware trigger function is only supported in single-cycle scan mode. If hardware trigger mode, the ADST bit (ADCR[11]) can be set to 1 by the selected hardware trigger source.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PTEN : PDMA Transfer Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIFFEN : Differential Input Mode Control
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADST : A/D Conversion Start ADST bit can be set to 1 from three sources: software, PWM Center-aligned trigger and external pin STADC. ADST will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan mode, A/D conversion is continuously performed until software writes 0 to this bit or chip reset.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMOF : A/D Differential Input Mode Output Format
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN : Analog Input Channel Enable Bit Set CHEN[7:0] to enable the corresponding analog input channel 7 ~ 0. If DIFFEN bit (ADCR[10]) is set to 1, only the even number channels need to be enabled.
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRESEL : Analog Input Channel 7 Selection
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN1 : Analog Input Channel Enable Bit 1 Set CHEN[14:10] to enable the corresponding analog input channel 11 ~ 8. If DIFFEN bit (ADCR[10]) is set to 1, only the even number channels need to be enabled.
bits : 10 - 13 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPEN : Compare Enable Bit Set this bit to 1 to enable ADC controller to compare CMPD (ADCMPR0/1[27:16]) with specified channel conversion result when converted data is loaded into ADDR register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPIE : Compare Interrupt Enable Bit If the compare function is enabled and the compare condition matches the setting of CMPCOND (ADCMPR0/1[2]) and CMPMATCNT (ADCMPR0/1[11:8]), CMPF0/1 bit (ADSR[1]/[2]) will be asserted, in the meanwhile, if CMPIE (ADCMPR0/1[1]) is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCOND : Compare Condition Note: When the internal counter reaches the value to (CMPMATCNT (ADCMPR0/1[11:8])+1), the CMPF0/1 bit (ADSR[1]/[2]) will be set.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCH : Compare Channel Selection
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPMATCNT : Compare Match Count When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADCMPR0/1[2]), the internal match counter will increase 1, The comparing data must successively matched with the compare condition. Once any comparing data does not match during the comparing, the internal counter will clear to 0. When the internal counter reaches the value to (CMPMATCNT (ADCMPR0/1[11:8]) +1), the CMPF0/1 bit (ADSR[1]/[2]) will be set.
bits : 8 - 11 (4 bit)
access : read-write

CMPD : Comparison Data The 12-bit data is used to compare with conversion result of specified channel. When DMOF bit (ADCR[31]) is set to 0, ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format. When DMOF bit (ADCR[31]) is set to 1, ADC comparator compares CMPD with conversion result with 2'complement format. CMPD should be filled in 2'complement format.
bits : 16 - 27 (12 bit)
access : read-write

ADF : A/D Conversion End Flag A status flag that indicates the end of A/D conversion. ADF is set to 1 at these two conditions: 1. When A/D conversion ends in Single mode. 2. When A/D conversion ends on all specified channels in Scan mode. This flag can be cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write

CMPF0 : Compare Flag When the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPF1 : Compare Flag When the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSY : BUSY/IDLE This bit is mirror of as ADST bit (ADCR[11]). It is read only.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHANNEL : Current Conversion Channel It is read only.
bits : 4 - 7 (4 bit)
access : read-write

VALID0 : Data Valid Flag It is a mirror of VALID bit (ADDR0~7[17]). It is read only.
bits : 8 - 15 (8 bit)
access : read-write

OVERRUN0 : Overrun Flag It is a mirror to OVERRUN bit (ADDR0~7[16]). It is read only.
bits : 16 - 23 (8 bit)
access : read-write

VALID1 : Data Valid Flag It is a mirror of VALID bit (ADDR8~11[17]). It is read only.
bits : 24 - 27 (4 bit)
access : read-write

OVERRUN1 : Overrun Flag It is a mirror to OVERRUN bit (ADDR8~11[16]). It is read only.
bits : 28 - 31 (4 bit)
access : read-write

AD_PDMA : ADC PDMA Current Transfer Data Register When PDMA transferring, read this register can monitor current PDMA transfer data. Current PDMA transfer data is the content of ADDR0 ~ ADDR11. This is a read only register.
bits : 0 - 17 (18 bit)
access : read-only