SYS_PDID (PDID)

SYS_IPRST2 (IPRST2)

SYS_REGLCTL (REGLCTL)

SYS_BODCTL (BODCTL)

SYS_IVSCTL (IVSCTL)

SYS_PORDISAN (PORDISAN)

SYS_PORCTL (PORCTL)

SYS_VREFCTL (VREFCTL)

SYS_GPA_MFP0 (GPA_MFP0)

SYS_GPA_MFP1 (GPA_MFP1)

SYS_RSTSTS (RSTSTS)

SYS_GPB_MFP1 (GPB_MFP1)

SYS_GPC_MFP0 (GPC_MFP0)

SYS_GPC_MFP1 (GPC_MFP1)

SYS_GPD_MFP0 (GPD_MFP0)

SYS_GPD_MFP1 (GPD_MFP1)

SYS_IPRST0 (IPRST0)

SYS_GPA_MFOS (GPA_MFOS)

SYS_GPB_MFOS (GPB_MFOS)

SYS_GPC_MFOS (GPC_MFOS)

SYS_GPD_MFOS (GPD_MFOS)

SYS_IPRST1 (IPRST1)

SYS_SRAM_BISTCTL (SRAM_BISTCTL)

SYS_SRAM_BISTSTS (SRAM_BISTSTS)

SYS_MODCTL (MODCTL)

SYS_HIRCTRIMCTL (HIRCTRIMCTL)

SYS_HIRCTRIMIEN (HIRCTRIMIEN)

SYS_HIRCTRIMSTS (HIRCTRIMSTS)

PDID : Part Device Identification Number (Read Only) This register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only

USCI0RST : USCI0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USCI1RST : USCI1 Controller Reset
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DAC0RST : DAC0 Controller Reset
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0RST : PWM0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REGLCTL : Register Lock Control Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. REGLCTL[0] Register Lock Control Disable Index (Read Only)
bits : 0 - 7 (8 bit)
access : write-only

Enumeration:

End of enumeration elements list.

BODEN : Brown-out Detector Enable Bit (Write Protect) The default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]). Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Reset by powr on reset.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODRSTEN : Brown-out Reset Enable Bit (Write Protect) The default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit . Note 1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. Note 3: Reset by powr on reset.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODIF : Brown-out Detector Interrupt Flag Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODLPM : Brown-out Detector Low Power Mode (Write Protect) Note 1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODOUT : Brown-out Detector Output Status It means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled, this bit always responds 0000.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVREN : Low Voltage Reset Enable Bit (Write Protect) The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. Note 1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (default). Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODDGSEL : Brown-out Detector Output De-glitch Time Select (Write Protect) Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRDGSEL : LVR Output De-glitch Time Select (Write Protect) Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODVL : Brown-out Detector Threshold Voltage Selection (Write Protect) The default value is set by Flash controller user configuration register CBOV (CONFIG0 [22:21]). Note: This bit is write protected. Refer to the SYS_REGLCTL register. Note : reset by powr on reset
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VTEMPEN : Temperature Sensor Enable Bit This bit is used to enable/disable temperature sensor function. Note: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result. Please refer to ADC function chapter for details.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POROFFAN : Power-on Reset Enable Bit (Write Protect) After powered on, User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field. The analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 15 (16 bit)
access : read-write

POROFF : Power-on Reset Enable Bit (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 15 (16 bit)
access : read-write

VREFCTL : VREF Control Bits (Write Protect) Note 1: GPA1 needs to keep folating if Internal voltage reference is enabled. Note 2: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCPRESEL : ADC Voltage Reference Note: These bits is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRELOADSEL : Pre-load Timing Selection (Write Protect) Note: These bits is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA0MFP : PA.0 Multi-function Pin Selection
bits : 0 - 7 (8 bit)
access : read-write

GPA1MFP : PA.1 Multi-function Pin Selection
bits : 8 - 15 (8 bit)
access : read-write

GPA2MFP : PA.2 Multi-function Pin Selection
bits : 16 - 23 (8 bit)
access : read-write

GPA3MFP : PA.3 Multi-function Pin Selection
bits : 24 - 31 (8 bit)
access : read-write

GPA4MFP : PA.4 Multi-function Pin Selection
bits : 0 - 7 (8 bit)
access : read-write

GPA5MFP : PA.5 Multi-function Pin Selection
bits : 8 - 15 (8 bit)
access : read-write

PORF : POR Reset Flag The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINRF : NRESET Pin Reset Flag The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTRF : WDT Reset Flag The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. Note 1: Write 1 to clear this bit to 0. Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRF : LVR Reset Flag The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODRF : BOD Reset Flag The BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSRF : System Reset Flag The system reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURF : CPU Reset Flag The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex- M0 Core and Flash Memory Controller (FMC). Note: Write to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPULKRF : CPU Lockup Reset Flag Note: Write 1 to clear this bit to 0. Note 2: When CPU lockup happened under ICE is connected, This flag will set to 1 but chip will not reset.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB4MFP : PB.4 Multi-function Pin Selection
bits : 0 - 7 (8 bit)
access : read-write

GPB5MFP : PB.5 Multi-function Pin Selection
bits : 8 - 15 (8 bit)
access : read-write

GPB6MFP : PB.6 Multi-function Pin Selection
bits : 16 - 23 (8 bit)
access : read-write

GPB7MFP : PB.7 Multi-function Pin Selection
bits : 24 - 31 (8 bit)
access : read-write

GPC0MFP : PC.0 Multi-function Pin Selection
bits : 0 - 7 (8 bit)
access : read-write

GPC1MFP : PC.1 Multi-function Pin Selection
bits : 8 - 15 (8 bit)
access : read-write

GPC2MFP : PC.2 Multi-function Pin Selection
bits : 16 - 23 (8 bit)
access : read-write

GPC3MFP : PC3 Multi-function Pin Selection
bits : 24 - 31 (8 bit)
access : read-write

GPC4MFP : PC.4 Multi-function Pin Selection
bits : 0 - 7 (8 bit)
access : read-write

GPC5MFP : PC.5 Multi-function Pin Selection
bits : 8 - 15 (8 bit)
access : read-write

GPC6MFP : PC.6 Multi-function Pin Selection
bits : 16 - 23 (8 bit)
access : read-write

GPC7MFP : PC.7Multi-function Pin Selection
bits : 24 - 31 (8 bit)
access : read-write

GPD0MFP : PD.0 Multi-function Pin Selection
bits : 0 - 7 (8 bit)
access : read-write

GPD1MFP : PD.1 Multi-function Pin Selection
bits : 8 - 15 (8 bit)
access : read-write

GPD2MFP : PD.2 Multi-function Pin Selection
bits : 16 - 23 (8 bit)
access : read-write

GPD3MFP : PD3 Multi-function Pin Selection
bits : 24 - 31 (8 bit)
access : read-write

GPD4MFP : PD.4 Multi-function Pin Selection
bits : 0 - 7 (8 bit)
access : read-write

GPD5MFP : PD.5 Multi-function Pin Selection
bits : 8 - 15 (8 bit)
access : read-write

GPD6MFP : PD.6 Multi-function Pin Selection
bits : 16 - 23 (8 bit)
access : read-write

GPD7MFP : PD.7Multi-function Pin Selection
bits : 24 - 31 (8 bit)
access : read-write

CHIPRST : Chip One-shot Reset (Write Protect) Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from Flash are also reload. About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2 Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: Reset by powr on reset.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURST : Processor Core One-shot Reset (Write Protect) Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMARST : PDMA Controller Reset (Write Protect) Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HDIV_RST : HDIV Controller Reset (Write Protect) Set this bit to 1 will generate a reset signal to the hardware divider. User need to set this bit to 0 to release from the reset state. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRCRST : CRC Calculation Controller Reset (Write Protect) Set this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS0 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS1 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS2 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS3 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS4 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS5 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS6 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS7 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS8 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS9 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS10 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS11 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS12 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS13 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS14 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOS15 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin. If MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIORST : GPIO Controller Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2RST : Timer2 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR3RST : Timer3 Controller Reset
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP01RST : Analog Comparator 0/1 Controller Reset
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0RST : UART0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1RST : UART1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAN0RST : CAN0 Controller Reset
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCRST : ADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMABIST : PDMA BIST Enable Bit (Write Protect) This bit enables BIST test for PDMA RAM Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMABISTF : PDMA SRAM BIST Failed Flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PDMAEND : PDMA SRAM BIST Test Finish
bits : 23 - 23 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MODEN : Modulation Function Enable Bit This bit enables modulation funcion by modulating with PWM0 channel output and USCI0(USCI0_DAT0) or UART0(UART0_TXD) output.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODH : Modulation at Data High Select modulation pulse(PWM0) at high or low of UART0_TXD or USCI0_DAT0
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODPWMSEL : PWM0 Channel Select for Modulation Select the PWM0 channel to modulate with the UART0_TXD or USCI0_DAT0. 0000: PWM0 Channel 0 modulate with UART0_TXD. 0001: PWM0 Channel 1 modulate with UART0_TXD. 0010: PWM0 Channel 2 modulate with UART0_TXD. 0011: PWM0 Channel 3 modulete with UART0_TXD. 0100: PWM0 Channel 4 modulete with UART0_TXD. 0101: PWM0 Channel 5 modulete with UART0_TXD. 0110: Reserved. 0111: Reserved. 1000: PWM0 Channel 0 modulate with USCI0_DAT0. 1001: PWM0 Channel 1 modulate with USCI0_DAT0. 1010: PWM0 Channel 2 modulate with USCI0_DAT0. 1011: PWM0 Channel 3 modulete with USCI0_DAT0. 1100: PWM0 Channel 4 modulete with USCI0_DAT0. 1101: PWM0 Channel 5 modulete with USCI0_DAT0. 1110: Reserved. 1111: Reserved. Note: This bis is valid while MODEN (SYS_MODCTL[0]) is set to 1.
bits : 4 - 7 (4 bit)
access : read-write

FREQSEL : Trim Frequency Selection This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim. During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOOPSEL : Trim Calculation Loop Selection This field defines that trim value calculation is based on how many reference clocks. Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RETRYCNT : Trim Value Update Limitation Count This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. Once the HIRC locked, the internal trim value update counter will be reset. If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CESTOPEN : Clock Error Stop Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOUNDEN : Boundary Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REFCKSEL : Reference Clock Selection Note: If there is no reference clock (LXT) when the rc_trim is enabled, CLKERIF (SYS_HIRCTRIMCTL[2]) will be set to 1.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOUNDARY : Boundary Selection Fill the boundary range from 0x1 to 0x1F, 0x0 is reserved. Note: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enable.
bits : 16 - 20 (5 bit)
access : read-write

TFALIEN : Trim Failure Interrupt Enable Bit This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTRIMCTL[1:0]). If this bit is high and TFAILIF(SYS_HIRCTRIMSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKEIEN : Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. If this bit is set to1, and CLKERRIF(SYS_HIRCTRIMSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQLOCK : HIRC Frequency Lock Status This bit indicates the HIRC frequency is locked. This is a status bit and doesn't trigger any interrupt Write 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled. Note : Reset by powr on reset.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIF : Trim Failure Interrupt Status This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_HIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically. If this bit is set and TFAILIEN(SYS_HIRCIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0. Note : reset by powr on reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERIF : Clock Error Interrupt Status When the frequency relation between reference clock and 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy. Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_HIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_HIRCTRIMCTL[8]) is set to 1. If this bit is set and CLKEIEN(SYS_HIRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0. Note : reset by powr on reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVBDIF : Over Boundary Status When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. Note: Write 1 to clear this flag.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.