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NVIC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x80 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x200 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

NVIC_ISER0 (ISER0)

NVIC_ISPR0 (ISPR0)

NVIC_ICPR0 (ICPR0)

NVIC_IABR0 (IABR0)

NVIC_ICER0 (ICER0)


NVIC_ISER0 (ISER0)

IRQ0 ~ IRQ31 Set-enable Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISER0 NVIC_ISER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt Set Enable Bit The NVIC_ISER0 registers enable interrupts, and show which interrupts are enabled Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt Disabled

1 : 1

Interrupt Enabled

End of enumeration elements list.


NVIC_ISPR0 (ISPR0)

IRQ0 ~ IRQ31 Set-pending Control Register
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISPR0 NVIC_ISPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt Set-pending The NVIC_ISPR0 registers force interrupts into the pending state, and show which interrupts are pending Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt is not pending

1 : 1

Changes interrupt state to pending. Interrupt is pending

End of enumeration elements list.


NVIC_ICPR0 (ICPR0)

IRQ0 ~ IRQ31 Clear-pending Control Register
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICPR0 NVIC_ICPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALPEND

CALPEND : Interrupt Clear-pending The NVIC_ICPR0 registers remove the pending state from interrupts, and show which interrupts are pending Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt is not pending

1 : 1

Removes pending state an interrupt. Interrupt is pending

End of enumeration elements list.


NVIC_IABR0 (IABR0)

IRQ0 ~ IRQ31 Active Bit Register
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IABR0 NVIC_IABR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt Active Flags The NVIC_IABR0 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

interrupt not active

1 : 1

interrupt active

End of enumeration elements list.


NVIC_ICER0 (ICER0)

IRQ0 ~ IRQ31 Clear-enable Control Register
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICER0 NVIC_ICER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALENA

CALENA : Interrupt Clear Enable Bit The NVIC_ICER0 registers disable interrupts, and show which interrupts are enabled. Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt Disabled

1 : 1

Interrupt Disabled. Interrupt Enabled

End of enumeration elements list.



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