\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x60 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x70 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xB4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTEN : HXT Enable Bit (Write Protect)
Note 1: Reset by power on reset.
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Eexternal high speed crystal (HXT) Disabled
#1 : 1
External high speed crystal (HXT) Enabled
End of enumeration elements list.
LXTEN : LXT Enable Bit (Write Protect)
Note 1: Reset by power on reset.
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
External low speed crystal (LXT) Disabled
#1 : 1
External low speed crystal (LXT) Enabled
End of enumeration elements list.
HIRCEN : HIRC Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal high speed RC oscillator (HIRC) Disabled
#1 : 1
Internal high speed RC oscillator (HIRC) Enabled
End of enumeration elements list.
LIRCEN : LIRC Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal low speed RC oscillator (LIRC) Disabled
#1 : 1
Internal low speed RC oscillator (LIRC) Enabled
End of enumeration elements list.
PDWKDLY : Enable the Wake-up Delay Counter (Write Protect)
When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip works at external high speed crystal oscillator (HXT), and 512 clock cycles when chip works at internal high speed RC oscillator (HIRC).
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock cycles delay Disabled
#1 : 1
Clock cycles delay Enabled
End of enumeration elements list.
PDWKIEN : Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
Note 1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power-down mode wake-up interrupt Disabled
#1 : 1
Power-down mode wake-up interrupt Enabled
End of enumeration elements list.
PDWKIF : Power-down Mode Wake-up Interrupt Status
Set by 'Power-down wake-up event', it indicates that resume from Power-down mode'
The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.
Note 1: Write 1 to clear the bit to 0.
Note 2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
bits : 6 - 6 (1 bit)
access : read-write
PDEN : System Power-down Enable (Write Protect)
When this bit is set to 1, Power-down mode is enabled and chip keeps active utill the CPU sleep mode is also active and then the chip enters Power-down mode.
When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.
In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. If user disable LIRC before entering power-down mode, this bit should be set after LIRC disabled 50us.
In Power-down mode, system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip operating normally or chip in idle mode because of WFI command
#1 : 1
Chip enters Power-down mode instant or wait CPU sleep command WFI
End of enumeration elements list.
LXTGAIN : LXT Gain Control Bit (Write Protect)
Please refer to LXT Charateristic.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 24 - 26 (3 bit)
access : read-write
LXTSELXT : LXT Crystal Mode Selection
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
LXT works as external clock mode. PC.5 is configured as external clock input pin
#1 : 1
LXT works as crystal mode. PC.4 and PC.5 are configured as low speed crystal (LXT) pins
End of enumeration elements list.
HXTGAIN : HXT Gain Control Bit (Write Protect)
Please refer to HXT Charateristic.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 28 - 30 (3 bit)
access : read-write
HXTSELXT : HXT Crystal Mode Selection
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
HXT works as external clock mode. PA.5 is configured as external clock input pin
#1 : 1
HXT works as crystal mode. PA.4 and PA.5 are configured as high speed crystal (HXT) pins
End of enumeration elements list.
Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKSEL : HCLK Clock Source Selection (Write Protect)
Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Reset by power on reset
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HXT
#001 : 1
Clock source from LXT
#011 : 3
Clock source from LIRC
#111 : 7
Clock source from HIRC
End of enumeration elements list.
STCLKSEL : Cortex-M0 SysTick Clock Source Selection (Write Protect)
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HXT
#001 : 1
Clock source from LXT
#010 : 2
Clock source from HXT/2
#011 : 3
Clock source from HCLK/2
#111 : 7
Clock source from HIRC/2
End of enumeration elements list.
Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTSEL : Watchdog Timer Clock Source Selection (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2. It will be forced to 11 when CONFIG0[31], CONFIG0[4], CONFIG0[3] are all ones.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#01 : 1
Clock source from external low speed crystal oscillator (LXT)
#10 : 2
Clock source from HCLK/2048
#11 : 3
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
WWDTSEL : Window Watchdog Timer Clock Source Selection (Write Protect)
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#10 : 2
Clock source from HCLK/2048
#11 : 3
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
CLKOSEL : Clock Divider Clock Source Selection
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from HCLK
#100 : 4
Clock source from internal low speed RC oscillator (LIRC)
#101 : 5
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR0SEL : TIMER0 Clock Source Selection
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK0
#011 : 3
Clock source from external clock T0 pin
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR1SEL : TIMER1 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK0
#011 : 3
Clock source from external clock T1 pin
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR2SEL : TIMER2 Clock Source Selection
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK1
#011 : 3
Clock source from external clock T2 pin
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR3SEL : TIMER3 Clock Source Selection
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK1
#011 : 3
Clock source from external clock T3 pin
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
UART0SEL : UART0 Clock Source Selection
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#010 : 2
Clock source from external low speed crystal oscillator (LXT)
#011 : 3
Clock source from internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from PCLK0
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
UART1SEL : UART1 Clock Source Selection
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#010 : 2
Clock source from external low speed crystal oscillator (LXT)
#011 : 3
Clock source from internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from PCLK1
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
Clock Source Select Control Register 2
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCSEL : ADC Clock Source Selection
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external high speed crystal oscillator (HXT) clock
#01 : 1
Reserved.
#10 : 2
Clock source from PCLK1
#11 : 3
Clock source from internal high speed RC oscillator (HIRC) clock
End of enumeration elements list.
Clock Divider Number Register 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write
UART0DIV : UART0 Clock Divide Number From UART0 Clock Source
bits : 8 - 11 (4 bit)
access : read-write
UART1DIV : UART1 Clock Divide Number From UART1 Clock Source
bits : 12 - 15 (4 bit)
access : read-write
ADCDIV : ADC Clock Divide Number From ADC Clock Source
bits : 16 - 23 (8 bit)
access : read-write
APB Clock Divider Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APB0DIV : APB0 Clock DIvider
APB0 clock can be divided from HCLK
Others: Reserved.
bits : 0 - 2 (3 bit)
access : read-write
APB1DIV : APB1 Clock DIvider
APB1 clock can be divided from HCLK
Others: Reserved.
bits : 4 - 6 (3 bit)
access : read-write
AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMACKEN : PDMA Controller Clock Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA peripheral clock Disabled
#1 : 1
PDMA peripheral clock Enabled
End of enumeration elements list.
ISPCKEN : Flash ISP Controller Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash ISP peripheral clock Disabled
#1 : 1
Flash ISP peripheral clock Enabled
End of enumeration elements list.
HDIV_EN : Divider Controller Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Divider controller peripheral clock Disabled
#1 : 1
Divider controller peripheral clock Enabled
End of enumeration elements list.
CRCCKEN : CRC Generator Controller Clock Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRC peripheral clock Disabled
#1 : 1
CRC peripheral clock Enabled
End of enumeration elements list.
Clock Status Monitor Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HXTSTB : HXT Clock Source Stable Flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock is not stable or disabled
#1 : 1
External high speed crystal oscillator (HXT) clock is stable and enabled
End of enumeration elements list.
LXTSTB : LXT Clock Source Stable Flag (Read Only)
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
External low speed crystal oscillator (LXT) clock is not stable or disabled
#1 : 1
External low speed crystal oscillator (LXT) clock is stabled and enabled
End of enumeration elements list.
LIRCSTB : LIRC Clock Source Stable Flag (Read Only)
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal low speed RC oscillator (LIRC) clock is not stable or disabled
#1 : 1
Internal low speed RC oscillator (LIRC) clock is stable and enabled
End of enumeration elements list.
HIRCSTB : HIRC Clock Source Stable Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal high speed RC oscillator (HIRC) clock is not stable or disabled
#1 : 1
Internal high speed RC oscillator (HIRC) clock is stable and enabled
End of enumeration elements list.
CLKSFAIL : Clock Switching Fail Flag (Read Only)
This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.
Note: Write 1 to clear the bit to 0.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Clock switching success
#1 : 1
Clock switching failure
End of enumeration elements list.
Clock Output Control Register
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Clock Output Frequency Selection
The formula of output frequency is
Fin is the input clock frequency.
Fout is the frequency of divider output clock.
N is the 4-bit value of FREQSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write
CLKOEN : Clock Output Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Output function Disabled
#1 : 1
Clock Output function Enabled
End of enumeration elements list.
DIV1EN : Clock Output Divide One Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Output will output clock with source frequency divided by FREQSEL
#1 : 1
Clock Output will output clock with source frequency
End of enumeration elements list.
Clock Fail Detector Control Register
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFDEN : HXT Clock Fail Detector Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock fail detector Disabled
#1 : 1
External high speed crystal oscillator (HXT) clock fail detector Enabled
End of enumeration elements list.
HXTFIEN : HXT Clock Fail Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock fail interrupt Disabled
#1 : 1
External high speed crystal oscillator (HXT) clock fail interrupt Enabled
End of enumeration elements list.
LXTFDEN : LXT Clock Fail Detector Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
External low speed crystal oscillator (LXT) clock fail detector Disabled
#1 : 1
External low speed crystal oscillator (LXT) clock fail detector Enabled
End of enumeration elements list.
LXTFIEN : LXT Clock Fail Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
External low speed crystal oscillator (LXT) clock fail interrupt Disabled
#1 : 1
External low speed crystal oscillator (LXT) clock fail interrupt Enabled
End of enumeration elements list.
HXTFQDEN : HXT Clock Frequency Range Detector Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock frequency range detector Disabled
#1 : 1
External high speed crystal oscillator (HXT) clock frequency range detector Enabled
End of enumeration elements list.
HXTFQIEN : HXT Clock Frequency Range Detector Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled
#1 : 1
External high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled
End of enumeration elements list.
Clock Fail Detector Status Register
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFIF : HXT Clock Fail Interrupt Flag (Write Protect)
Note: Write 1 to clear the bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock is normal
#1 : 1
External high speed crystal oscillator (HXT) clock stops
End of enumeration elements list.
LXTFIF : LXT Clock Fail Interrupt Flag (Write Protect)
Note: Write 1 to clear the bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
External low speed crystal oscillator (LXT) clock is normal
#1 : 1
External low speed crystal oscillator (LXT) stops
End of enumeration elements list.
HXTFQIF : HXT Clock Frequency Range Detector Interrupt Flag (Write Protect)
Note: Write 1 to clear the bit to 0.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock frequency is normal
#1 : 1
External high speed crystal oscillator (HXT) clock frequency is abnormal
End of enumeration elements list.
Clock Frequency Range Detector Upper Boundary Register
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPERBD : HXT Clock Frequency Range Detector Upper Boundary Value
The bits define the maximum value of frequency range detector window.
When HXT frequency is higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will be set to 1.
bits : 0 - 9 (10 bit)
access : read-write
Clock Frequency Range Detector Lower Boundary Register
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOWERBD : HXT Clock Frequency Range Detector Lower Boundary Value
The bits define the minimum value of frequency range detector window.
When HXT frequency is lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will be set to 1.
bits : 0 - 9 (10 bit)
access : read-write
APB Devices Clock Enable Control Register 0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTCKEN : Watchdog Timer Clock Enable Bit (Write Protect)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: This bit is reset by power on reset, Watchdog reset or software chip reset.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog timer clock Disabled
#1 : 1
Watchdog timer clock Enabled
End of enumeration elements list.
TMR0CKEN : Timer0 Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 clock Disabled
#1 : 1
Timer0 clock Enabled
End of enumeration elements list.
TMR1CKEN : Timer1 Clock Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 clock Disabled
#1 : 1
Timer1 clock Enabled
End of enumeration elements list.
TMR2CKEN : Timer2 Clock Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 clock Disabled
#1 : 1
Timer2 clock Enabled
End of enumeration elements list.
TMR3CKEN : Timer3 Clock Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 clock Disabled
#1 : 1
Timer3 clock Enabled
End of enumeration elements list.
CLKOCKEN : CLKO Clock Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
CLKO clock Disabled
#1 : 1
CLKO clock Enabled
End of enumeration elements list.
ACMP01CKEN : Analog Comparator 0/1 Clock Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog comparator 0/1 clock Disabled
#1 : 1
Analog comparator 0/1 clock Enabled
End of enumeration elements list.
UART0CKEN : UART0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 clock Disabled
#1 : 1
UART0 clock Enabled
End of enumeration elements list.
UART1CKEN : UART1 Clock Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 clock Disabled
#1 : 1
UART1 clock Enabled
End of enumeration elements list.
CAN0CKEN : CAN0 Clock Enable Bit
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
CAN0 clock Disabled
#1 : 1
CAN0 clock Enabled
End of enumeration elements list.
ADCCKEN : Analog-digital-converter Clock Enable Bit
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC clock Disabled
#1 : 1
ADC clock Enabled
End of enumeration elements list.
HXT Filter Select Control Register
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFSEL : HXT Filter Select
Note: This bit should not be changed during HXT running.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
HXT frequency is greater than12 MHz
#1 : 1
HXT frequency is less than or equal to 12 MHz
End of enumeration elements list.
APB Devices Clock Enable Control Register 1
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USCI0CKEN : USCI0 Clock Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI0 clock Disabled
#1 : 1
USCI0 clock Enabled
End of enumeration elements list.
USCI1CKEN : USCI1 Clock Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI1 clock Disabled
#1 : 1
USCI1 clock Enabled
End of enumeration elements list.
DACCKEN : DAC Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC clock Disabled
#1 : 1
DAC clock Enabled
End of enumeration elements list.
PWM0CKEN : PWM0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0 clock Disabled
#1 : 1
PWM0 clock Enabled
End of enumeration elements list.
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