FMC_ISPCTL (ISPCTL)

FMC_ISPTRG (ISPTRG)

FMC_DFBA (DFBA)

FMC_ISPADDR (ISPADDR)

FMC_ISPSTS (ISPSTS)

FMC_ISPDAT (ISPDAT)

FMC_ISPCMD (ISPCMD)

ISPEN : ISP Enable Bit (Write Protect) Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BS : Boot Selection (Write Protect) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

APUEN : APROM Update Enable Bit (Write Protect) Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGUEN : CONFIG Update Enable Bit (Write Protect) Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDUEN : LDROM Update Enable Bit (Write Protect) LDROM update enable bit. Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect) This bit is set by hardware when a triggered ISP meets any of the following conditions: APROM writes to itself if APUEN is set to 0. LDROM writes to itself if LDUEN is set to 0. CONFIG is erased/programmed if CFGUEN is set to 0. Page Erase command at LOCK mode with ICE connection. Erase or Program command at brown-out detected. Destination address is illegal, such as over an available range. Invalid ISP commands. This bit needs to be cleared by writing 1 to it. Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

ISPGO : ISP Start Trigger (Write Protect) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFBA : Data Flash Base Address This register indicates Data Flash start address. It is a read only register. The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1.
bits : 0 - 31 (32 bit)
access : read-only

ISPADDR : ISP Address The M0A21/M0A23 is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. For CRC32 Checksum Calculation command, this field is the Flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation. 16/32 Kbytes Flash: ISPADR[8:0] must be kept all 0 for Vector Page Remap Command.
bits : 0 - 31 (32 bit)
access : read-write

ISPBUSY : ISP BUSY (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CBS : Boot Selection of CONFIG (Read Only) This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect) This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions: APROM writes to itself if APUEN is set to 0. LDROM writes to itself if LDUEN is set to 0. CONFIG is erased/programmed if CFGUEN is set to 0. Page Erase command at LOCK mode with ICE connection Erase or Program command at brown-out detected Destination address is illegal, such as over an available range. Invalid ISP commands
bits : 6 - 6 (1 bit)
access : read-write

VECMAP : Vector Page Mapping Address (Read Only) All access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}. VECMAP [18:12] should be 0.
bits : 9 - 29 (21 bit)
access : read-only

ISPDAT : ISP Data Write data to this register before ISP program operation. Read data from this register after ISP read operation.
bits : 0 - 31 (32 bit)
access : read-write

CMD : ISP CMD ISP command table is shown below: The other commands are invalid.
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.