PA_MODE

PA_PIN

PA_DBEN

PA_INTTYPE

PA_INTEN

PA_INTSRC

PA_SMTEN

PA_PUSEL

PA_DINOFF

PB_MODE

PB_DINOFF

GPIO_DBCTL (DBCTL)

GPIO_CLKON (CLKON)

PB_DOUT

PB_DATMSK

PB_PIN

PB_DBEN

PB_INTTYPE

PB_INTEN

PB_INTSRC

PB_SMTEN

PB_PUSEL

PA_DOUT

PC_MODE

PA0_PDIO

PA1_PDIO

PA2_PDIO

PA3_PDIO

PA4_PDIO

PA5_PDIO

PC_DINOFF

PB4_PDIO

PB5_PDIO

PB6_PDIO

PB7_PDIO

PC_DOUT

PC0_PDIO

PC1_PDIO

PC2_PDIO

PC3_PDIO

PC4_PDIO

PC5_PDIO

PC6_PDIO

PC7_PDIO

PC_DATMSK

PD0_PDIO

PD1_PDIO

PD2_PDIO

PD3_PDIO

PD4_PDIO

PD5_PDIO

PD6_PDIO

PD7_PDIO

PC_PIN

PC_DBEN

PC_INTTYPE

PC_INTEN

PC_INTSRC

PC_SMTEN

PC_PUSEL

PA_DATMSK

PD_MODE

PD_DINOFF

PD_DOUT

PD_DATMSK

PD_PIN

PD_DBEN

PD_INTTYPE

PD_INTEN

PD_INTSRC

PD_SMTEN

PD_PUSEL

MODE0 : Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE1 : Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE2 : Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE3 : Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE4 : Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE5 : Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE6 : Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE7 : Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored.
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE8 : Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE9 : Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored.
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE10 : Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE11 : Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE12 : Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored.
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE13 : Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored.
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE14 : Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE15 : Port A-D I/O Pin[n] Mode Control Determine each I/O mode of Px.n pins. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3: The GPA.3 is a input pin. Note 4: If MFOS is enabled then GPIO mode setting is ignored.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIN0 : Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PIN1 : Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PIN2 : Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PIN3 : Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PIN4 : Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PIN5 : Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PIN6 : Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PIN7 : Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PIN8 : Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PIN9 : Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PIN10 : Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PIN11 : Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PIN12 : Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PIN13 : Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PIN14 : Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PIN15 : Port A-D Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DBEN0 : Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN1 : Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN2 : Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN3 : Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN4 : Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN5 : Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN6 : Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN7 : Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN8 : Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN9 : Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN10 : Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN11 : Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN12 : Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN13 : Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN14 : Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN15 : Port A-D Pin[n] Input Signal De-bounce Enable Bit The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE0 : Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE1 : Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE2 : Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE3 : Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE4 : Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE5 : Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE6 : Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE7 : Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE8 : Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE9 : Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE10 : Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE11 : Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE12 : Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE13 : Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE14 : Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TYPE15 : Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN0 : Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN1 : Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN2 : Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN3 : Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN4 : Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN5 : Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN6 : Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN7 : Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN8 : Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN9 : Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN10 : Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN11 : Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN12 : Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN13 : Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN14 : Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN15 : Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the FLIEN (Px_INTEN[n]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN0 : Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN1 : Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN2 : Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN3 : Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN4 : Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN5 : Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN6 : Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN7 : Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN8 : Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN9 : Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN10 : Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN11 : Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN12 : Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN13 : Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN14 : Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN15 : Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC0 : Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC1 : Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC2 : Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC3 : Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC4 : Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC5 : Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC6 : Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC7 : Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC8 : Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC9 : Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC10 : Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC11 : Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC12 : Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC13 : Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC14 : Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC15 : Port A-D Pin[n] Interrupt Source Flag Write Operation: Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN0 : Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN1 : Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN2 : Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN3 : Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN4 : Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN5 : Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN6 : Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN7 : Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN8 : Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN9 : Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN10 : Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN11 : Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN12 : Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN13 : Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN14 : Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTEN15 : Port A-D Pin[n] Input Schmitt Trigger Enable Bit Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL0 : Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL1 : Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL2 : Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL3 : Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL4 : Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL5 : Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL6 : Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL7 : Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL8 : Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL9 : Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL10 : Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL11 : Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL12 : Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL13 : Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL14 : Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL15 : Port A-D Pin[n] Pull-up Enable Register Determine each I/O Pull-up of Px.n pins. Note 1: The independent pull-up control register only valid when MODEn set as input and open-drain mode even if I/O function is switched to multi-function pin. Ex: UARTx_RXD. Note2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF0 : Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF1 : Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF2 : Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF3 : Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF4 : Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF5 : Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF6 : Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF7 : Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF8 : Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF9 : Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF10 : Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF11 : Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF12 : Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF13 : Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF14 : Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF15 : Port A-D Pin[n] Digital Input Path Disable Bit Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. Note: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBCLKSEL : De-bounce Sampling Cycle Selection
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBCLKSRC : De-bounce Counter Clock Source Selection
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ICLKONx : Interrupt Clock on Mode Note: It is recommended to disable this bit to save system power if no special application concern. Each bit control each GPIO group.
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPxOn : GPIO Group Clock On-off The GPIO port clock can be disabled to reduce power consumption by setting GPIO_CLKON if the GPIO port isn't used. When GPxOn is set to 0 to diable GPIO port clock, the GPIO register, pin control and PDIO function are not workable. Only GPIO_CLKON and GPIO_DBCTL register can be updated
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT0 : Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT1 : Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT2 : Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT3 : Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT4 : Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT5 : Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT6 : Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT7 : Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT8 : Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT9 : Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT10 : Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT11 : Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT12 : Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT13 : Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT14 : Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT15 : Port A-D Pin[n] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. Note 1: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 2:The GPA.3 is a input pin.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDIO : GPIO Px.n Pin Data Input/Output Writing this bit can control one GPIO pin output value. Read this register to get GPIO pin status. For example, writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]), reading PA0_PDIO will return the value of PIN (PA_PIN[0]). Note 1: The writing operation will not be affected by register DATMSK (Px_DATMSK[n]). Note 2: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective. Note 3:The GPA.3 is a input pin.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.