\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x20 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :
Timer0 Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : Prescale Counter
Note: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
bits : 0 - 7 (8 bit)
access : read-write
TRGPDMA : Trigger PDMA Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer interrupt trigger PDMA Disabled
#1 : 1
Timer interrupt trigger PDMA Enabled
End of enumeration elements list.
INTRGEN : Inter-timer Trigger Mode Enable Bit
Setting this bit will enable the inter-timer trigger capture function.
The Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.
Note: For Timer1/3, this bit is ignored and the read back value is always 0.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inter-Timer Trigger mode Disabled
#1 : 1
Inter-Timer Trigger mode Enabled
End of enumeration elements list.
CAPSRC : Capture Pin Source Selection
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture Function source is from TMx_EXT (x= 0~3) pin
#1 : 1
Capture Function source is from internal ACMP output signal or LIRC. User can set INTERCAPSEL (TIMERx_EXTCTL[10:8]) to decide which internal ACMP output signal or LIRC is timer capture source
End of enumeration elements list.
TRGSSEL : Trigger Source Select Bit
This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer time-out interrupt signal is used to trigger PWM, DAC, ADC and PDMA
#1 : 1
Capture interrupt signal is used to trigger PWM, DAC, ADC and PDMA
End of enumeration elements list.
TRGPWM : Trigger PWM Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer interrupt trigger PWM Disabled
#1 : 1
Timer interrupt trigger PWM Enabled
End of enumeration elements list.
TRGDAC : Trigger DAC Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger DAC.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer interrupt trigger DAC Disabled
#1 : 1
Timer interrupt trigger DAC Enabled
End of enumeration elements list.
TRGADC : Trigger ADC Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer interrupt trigger ADC Disabled
#1 : 1
Timer interrupt trigger ADC Enabled
End of enumeration elements list.
TGLPINSEL : Toggle-output Pin Select
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Toggle mode output to Tx (Timer Event Counter Pin)
#1 : 1
Toggle mode output to Tx_EXT (Timer External Capture Pin)
End of enumeration elements list.
WKEN : Wake-up Function Enable Bit
If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up function Disabled if timer interrupt signal generated
#1 : 1
Wake-up function Enabled if timer interrupt signal generated
End of enumeration elements list.
EXTCNTEN : Event Counter Mode Enable Bit
This bit is for external counting pin function enabled.
Note 2: When TMR0/TMR2 INTRGEN is set to 1, this bit is forced to 1. When INTRGEN is 1 and TMR1/TMR3 CAPIF (TIMERx_EINTSTS[0]) is 1, this bit is forced to 0.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Event counter mode Disabled
#1 : 1
Event counter mode Enabled
End of enumeration elements list.
ACTSTS : Timer Active Status Bit (Read Only)
This bit indicates the 24-bit up counter status.
Note: This bit may be active when CNT 0 transition to CNT 1.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
24-bit up counter is not active
#1 : 1
24-bit up counter is active
End of enumeration elements list.
RSTCNT : Timer Counter Reset Bit
Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
Note: This bit will be auto cleared.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit
End of enumeration elements list.
OPMODE : Timer Counting Mode Select
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
#00 : 0
The timer controller is operated in One-shot mode
#01 : 1
The timer controller is operated in Periodic mode
#10 : 2
The timer controller is operated in Toggle-output mode
#11 : 3
The timer controller is operated in Continuous Counting mode
End of enumeration elements list.
INTEN : Timer Interrupt Enable Bit
Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer time-out interrupt Disabled
#1 : 1
Timer time-out interrupt Enabled
End of enumeration elements list.
CNTEN : Timer Counting Enable Bit
Note 3: Setting enable/disable this bit needs 2 * TMR_CLK period to become active. User can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stops/Suspends counting
#1 : 1
Starts counting
End of enumeration elements list.
ICEDEBUG : ICE Debug Mode Acknowledge Disable Bit (Write Protect)
TIMER counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement effects TIMER counting
#1 : 1
ICE debug mode acknowledgement Disabled
End of enumeration elements list.
Timer0 Capture Data Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPDAT : Timer Capture Data Register
When CAPEN (TIMERx_EXTCTL[3]) bit is set, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
bits : 0 - 23 (24 bit)
access : read-only
Timer0 External Control Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTPHASE : Timer External Count Phase
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
A falling edge of external counting pin will be counted
#1 : 1
A rising edge of external counting pin will be counted
End of enumeration elements list.
CAPEN : Timer Capture Enable Bit
This bit enables the capture input function.
Note: TMR1/TMR3 CAPEN will be forced to 1 when TMR0/TMR2 INTRGEN is enabled.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source Disabled
#1 : 1
Capture source Enabled
End of enumeration elements list.
CAPFUNCS : Capture Function Selection
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
External Capture Mode Enabled
#1 : 1
External Reset Mode Enabled
End of enumeration elements list.
CAPIEN : Timer External Capture Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
TMx_EXT (x= 0~3) pin, LIRC, or ACMP detection Interrupt Disabled
#1 : 1
TMx_EXT (x= 0~3) pin, LIRC, or ACMP detection Interrupt Enabled
End of enumeration elements list.
CAPDBEN : Timer External Capture Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled
#1 : 1
TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled
End of enumeration elements list.
CNTDBEN : Timer Counter Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
TMx (x= 0~3) pin de-bounce Disabled
#1 : 1
TMx (x= 0~3) pin de-bounce Enabled
End of enumeration elements list.
INTERCAPSEL : Internal Capture Source Selection to Trigger Capture Function
Note: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
Capture Function source is from internal ACMP0 output signal
#001 : 1
Capture Function source is from internal ACMP1 output signal
#101 : 5
Capture Function source is from LIRC
End of enumeration elements list.
CAPEDGE : Timer External Capture Pin Edge Detect
When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) will be set to 0.
Disable Single Pulse Mode :
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin.
Measure falling edge ( falling edge transfer on TMx_EXT (x= 0~3) pin
#001 : 1
Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin.
Measure rising edge ( rising edge transfer on TMx_EXT (x= 0~3) pin
#010 : 2
Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer
#011 : 3
Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer
#110 : 6
First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin.
Measure falling edge ( rising edge transfer on TMx_EXT (x= 0~3) pin
#111 : 7
First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin.
Measure rising edge ( falling edge transfer on TMx_EXT (x= 0~3) pin
End of enumeration elements list.
ECNTSSEL : Event Counter Source Selection to Trigger Event Counter Function
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Event Counter input source is from TMx (x= 0~3) pin
#1 : 1
Reserved.
End of enumeration elements list.
CASIGMEN : Capture Single Measure Mode Enable Bit
Note: these bits only available when CAPEN (TIMERx_EXTCTL[3]) is 1.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Single Measure Mode Disabled
#1 : 1
Single Measure Mode Enabled
End of enumeration elements list.
SIGST : Single Measure Start Bit
User can write 1'b1 to this bit to let timer start measure TMx_EXT pin. When capture measure event finishes this bit will auto clear by hardware.
bits : 21 - 21 (1 bit)
access : read-write
Timer0 External Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPIF : Timer External Capture Interrupt Flag
This bit indicates the timer external capture interrupt flag status.
Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
TMx_EXT (x= 0~3) pin interrupt did not occur
#1 : 1
TMx_EXT (x= 0~3) pin interrupt occurred
End of enumeration elements list.
Timer1 Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Comparator Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Interrupt Status Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Data Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Capture Data Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 External Control Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 External Interrupt Status Register
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer0 Comparator Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPDAT : Timer Comparator Value
CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
Note 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using the newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
bits : 0 - 23 (24 bit)
access : read-write
Timer0 Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIF : Timer Interrupt Flag
This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.
Note: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
CNT value matches the CMPDAT value
End of enumeration elements list.
TWKF : Timer Wake-up Flag
This bit indicates the interrupt wake-up flag status of timer.
Note: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer does not cause CPU wake-up
#1 : 1
CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated
End of enumeration elements list.
Timer0 Data Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Timer Data Register
Read this register to get CNT value. For example:
If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.
If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.
bits : 0 - 23 (24 bit)
access : read-only
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