UART_DAT

UART_MODEM

UART_MODEMSTS

UART_FIFOSTS

UART_INTSTS

UART_TOUT

UART_BAUD

UART_IRDA

UART_ALTCTL

UART_FUNCSEL

UART_LINCTL

UART_LINSTS

UART_BRCOMP

UART_INTEN

UART_WKCTL

UART_WKSTS

UART_DWKCOMP

UART_LINRTOUT

UART_LINWKCTL

UART_FIFO

UART_LINE

DAT : Data Receive/Transmit Buffer Write Operation: By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read Operation: By reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
bits : 0 - 7 (8 bit)
access : read-write

PARITY : Parity Bit Receive/Transmit Buffer Write Operation: By writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. Read Operation: If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit. Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
bits : 8 - 8 (1 bit)
access : read-write

RTS : nRTS (Request-to-send) Signal Control This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. Note1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. Note2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. Note3: Single-wire mode supports this feature.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTSACTLV : nRTS Pin Active Level This bit defines the active level state of nRTS pin output. Note1: Refer to Figure 6.1113 and Figure 6.1114 for UART function mode. Note2: Refer to Figure 6.1124 and Figure 6.1125 for RS-485 function mode. Note3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTSSTS : nRTS Pin Status (Read Only) This bit mirror from nRTS pin output of voltage logic status.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CTSDETF : Detect nCTS State Change Flag This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1. Note: This bit can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTSSTS : nCTS Pin Status (Read Only) This bit mirror from nCTS pin input of voltage logic status. Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CTSACTLV : nCTS Pin Active Level This bit defines the active level state of nCTS pin input. Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOVIF : RX Overflow Error Interrupt Flag This bit is set when RX FIFO overflow. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. Note: This bit can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABRDIF : Auto-baud Rate Detect Interrupt Flag This bit is set to logic '1' when auto-baud rate detect function is finished. Note: This bit can be cleared by writing '1' to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABRDTOIF : Auto-baud Rate Detect Time-out Interrupt Flag This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow. Note: This bit can be cleared by writing '1' to it.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDRDETF : RS-485 Address Byte Detect Flag Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. Note2: This bit can be cleared by writing '1' to it.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PEF : Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. Note: This bit can be cleared by writing '1' to it.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEF : Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note: This bit can be cleared by writing '1' to it.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BIF : Break Interrupt Flag This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits). Note: This bit can be cleared by writing '1' to it.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXPTR : RX FIFO Pointer (Read Only) This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one. The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
bits : 8 - 13 (6 bit)
access : read-only

RXEMPTY : Receiver FIFO Empty (Read Only) This bit initiate RX FIFO empty or not. Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXFULL : Receiver FIFO Full (Read Only) This bit initiates RX FIFO full or not. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXPTR : TX FIFO Pointer (Read Only) This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
bits : 16 - 21 (6 bit)
access : read-only

TXEMPTY : Transmitter FIFO Empty (Read Only) This bit indicates TX FIFO empty or not. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
bits : 22 - 22 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXFULL : Transmitter FIFO Full (Read Only) This bit indicates TX FIFO full or not. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
bits : 23 - 23 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXOVIF : TX Overflow Error Interrupt Flag If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. Note: This bit can be cleared by writing '1' to it.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXEMPTYF : Transmitter Empty Flag (Read Only) This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXIDLE : RX Idle Status (Read Only) This bit is set by hardware when RX is idle.
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXRXACT : TX and RX Active Status (Read Only) This bit indicates TX and RX are active or inactive. Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RDAIF : Receive Data Available Interrupt Flag When the number of bytes in the RX FIFO equals the RFITL then the RDAIF (UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled, the RDA interrupt will be generated. Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

THREIF : Transmit Holding Register Empty Interrupt Flag This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLSIF : Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MODEMIF : MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0]).
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXTOIF : RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUFERRIF : Buffer Error Interrupt Flag (Read Only) This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared if both of RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF (UART_FIFOSTS[0]) and TXOVIF (UART_FIFOSTS[24]).
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

WKIF : UART Wake-up Interrupt Flag (Read Only) This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF (UART_WKSTS[0]) is set to 1. Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LINIF : LIN Bus Interrupt Flag Note: This bit is cleared when SLVHDETF (UART_LINSTS[0]), SLVHEF (UART_LINSTS[1]), SLVIDPEF (UART_LINSTS[2]), SLVHTOF (UART_LINSTS[4]), RTOUTF (UART_LINSTS[5]), BRKDETF (UART_LINSTS[8]), and BITEF (UART_LINSTS[9]) all are cleared and software writing '1' to LINIF (UART_INTSTS[7]).
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDAINT : Receive Data Available Interrupt Indicator (Read Only) This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

THREINT : Transmit Holding Register Empty Interrupt Indicator (Read Only) This bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1.
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RLSINT : Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1.
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MODEMINT : MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and MODEMIF (UART_INTSTS[3]) are both set to 1
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXTOINT : RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1.
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUFERRINT : Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_ INTSTS[5]) are both set to 1.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

WKINT : UART Wake-up Interrupt Indicator (Read Only) This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LININT : LIN Bus Interrupt Indicator (Read Only) This bit is set if LINIEN (UART_INTEN[8]) and LINIF (UART_INTSTS[7]) are both set to 1.
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SWBEIF : Single-wire Bit Error Detection Interrupt Flag This bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode. Note1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode. Note2: This bit can be cleared by writing '1' to it.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HWRLSIF : PDMA Mode Receive Line Status Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HWMODIF : PDMA Mode MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0]).
bits : 19 - 19 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HWTOIF : PDMA Mode RX Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HWBUFEIF : PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
bits : 21 - 21 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXENDIF : Transmitter Empty Interrupt Flag This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWBEINT : Single-wire Bit Error Detect Interrupt Indicator (Read Only) This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HWRLSINT : PDMA Mode Receive Line Status Interrupt Indicator (Read Only) This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF (UART_INTSTS[18]) are both set to 1.
bits : 26 - 26 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HWMODINT : PDMA Mode MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF (UART_INTSTS[19]) are both set to 1.
bits : 27 - 27 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HWTOINT : PDMA Mode RX Time-out Interrupt Indicator (Read Only) This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF (UART_INTSTS[20]) are both set to 1.
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HWBUFEINT : PDMA Mode Buffer Error Interrupt Indicator (Read Only) This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXENDINT : Transmitter Empty Interrupt Indicator (Read Only) This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF (UART_INTSTS[22]) are both set to 1.
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRINT : Auto-baud Rate Interrupt Indicator (Read Only) This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOIC : Time-out Interrupt Comparator
bits : 0 - 7 (8 bit)
access : read-write

DLY : TX Delay Time Value This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
bits : 8 - 15 (8 bit)
access : read-write

BRD : Baud Rate Divider The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.114.
bits : 0 - 15 (16 bit)
access : read-write

EDIVM1 : Extra Divider for BAUD Rate Mode 1 This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.114.
bits : 24 - 27 (4 bit)
access : read-write

BAUDM0 : BAUD Rate Mode Selection Bit 0 This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.114.
bits : 28 - 28 (1 bit)
access : read-write

BAUDM1 : BAUD Rate Mode Selection Bit 1 This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.114. Note: In IrDA mode must be operated in mode 0.
bits : 29 - 29 (1 bit)
access : read-write

TXEN : IrDA Receiver/Transmitter Selection Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXINV : IrDA Inverse Transmitting Output Signal Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXINV : IrDA Inverse Receive Input Signal Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKFL : UART LIN Break Field Length This field indicates a 4-bit LIN TX break field count. Note1: This break field length is BRKFL + 1.
bits : 0 - 3 (4 bit)
access : read-write

LINRXEN : LIN RX Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINTXEN : LIN TX Break Mode Enable Bit Note: When TX break field transfer operation finished, this bit will be cleared automatically.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485NMM : RS-485 Normal Multi-drop Operation Mode (NMM) Note: It cannot be active with RS-485_AAD operation mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485AAD : RS-485 Auto Address Detection Operation Mode (AAD) Note: It cannot be active with RS-485_NMM operation mode.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485AUD : RS-485 Auto Direction Function (AUD) Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDRDEN : RS-485 Address Detection Enable Bit This bit is used to enable RS-485 Address Detection mode. Note: This bit is used for RS-485 any operation mode.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABRIF : Auto-baud Rate Interrupt Flag (Read Only) This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF (UART_FIFOSTS[1]).
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRDEN : Auto-baud Rate Detect Enable Bit Note : This bit is cleared automatically after auto-baud detection is finished.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABRDBITS : Auto-baud Rate Detect Bit Length Note : The calculation of bit number includes the START bit.
bits : 19 - 20 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDRMV : Address Match Value This field contains the RS-485 address match values. Note: This field is used for RS-485 auto address detection mode.
bits : 24 - 31 (8 bit)
access : read-write

FUNCSEL : Function Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXRXDIS : TX and RX Disable Bit Setting this bit can disable TX and RX. Note: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DGE : Deglitch Enable Bit Note: When this bit is set to logic 1, any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLVEN : LIN Slave Mode Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLVHDEN : LIN Slave Header Detection Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLVAREN : LIN Slave Automatic Resynchronization Mode Enable Bit Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1). Note3: The control and interactions of this field are explained in 6.11.5.10 (Slave mode with automatic resynchronization).
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLVDUEN : LIN Slave Divider Update Method Enable Bit Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) Note3: The control and interactions of this field are explained in 6.11.5.10 (Slave mode with automatic resynchronization).
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MUTE : LIN Mute Mode Enable Bit Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.11.5.10 (LIN slave mode).
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTOUTEN : LIN Response Time-out Detection Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SENDH : LIN TX Send Header Enable Bit The LIN TX header can be 'break field' or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]). Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL[7]) user can read/write it by setting LINTXEN (UART_ALTCTL[7]) or SENDH (UART_LINCTL[8]). Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IDPEN : LIN ID Parity Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKDETEN : LIN Break Detection Enable Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINRXOFF : LIN Receiver Disable Bit
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BITERREN : Bit Error Detect Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKFL : LIN Break Field Length This field indicates a 4-bit LIN TX break field count. Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]). Note2: This break field length is BRKFL + 1.
bits : 16 - 19 (4 bit)
access : read-write

BSL : LIN Break/Sync Delimiter Length Note: This bit used for LIN master to sending header field.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSEL : LIN Header Select
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PID : LIN PID Bits If the parity generated by hardware, user fill ID0~ID5 (PID[29:24]), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field. Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first). Note2: This field can be used for LIN master mode or slave mode.
bits : 24 - 31 (8 bit)
access : read-write

SLVHDETF : LIN Slave Header Detection Flag This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it. Note3: When enable ID parity check IDPEN (UART_LINCTL[9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLVHEF : LIN Slave Header Error Flag This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field', 'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode', 'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLVIDPEF : LIN Slave ID Parity Error Flag This bit is set by hardware when receipted frame ID parity is not correct.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLVSYNCF : LIN Slave Sync Field This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit. Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLVHTOF : LIN Slave Header Time-out Flag This bit is set by hardware when a LIN header reception time-out is detected in LIN slave mode and be cleared by writing 1 to it. When this bit is set, SLVHEF (UART_LINSTS[1]) will also be set.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTOUTF : LIN Response Time-out Flag This bit is set when no LIN response received and the time-out counter equal to or bigger than LINRTOIC (UART_LINRTOUT[23:0]). If LINIEN (UART_INTEN[8]) is enabled, the LIN Bus Interrupt will be generated. Note1: This bit can be cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKDETF : LIN Break Detection Flag This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BITEF : Bit Error Detect Status Flag At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRCOMP : Baud Rate Compensation Patten These 9-bits are used to define the relative bit is compensated or not. BRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8]).
bits : 0 - 8 (9 bit)
access : read-write

BRCOMPDEC : Baud Rate Compensation Decrease
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDAIEN : Receive Data Available Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

THREIEN : Transmit Holding Register Empty Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLSIEN : Receive Line Status Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODEMIEN : Modem Status Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTOIEN : RX Time-out Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUFERRIEN : Buffer Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKIEN : Wake-up Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINIEN : LIN Bus Interrupt Enable Bit Note: This bit is used for LIN function mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOCNTEN : Receive Buffer Time-out Counter Enable Bit
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATORTSEN : nRTS Auto-flow Control Enable Bit Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATOCTSEN : nCTS Auto-flow Control Enable Bit Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXPDMAEN : TX PDMA Enable Bit Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXPDMAEN : RX PDMA Enable Bit This bit can enable or disable RX PDMA service. Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF (UART_FIFOSTS[6]), Frame Error Flag FEF (UART_FIFO[5]) or Parity Error Flag PEF (UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWBEIEN : Single-wire Bit Error Detection Interrupt Enable Bit Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT (UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF (UART_INTSTS[16]) is set. Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABRIEN : Auto-baud Rate Interrupt Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXENDIEN : Transmitter Empty Interrupt Enable Bit If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKCTSEN : nCTS Wake-up Enable Bit Note:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKDATEN : Incoming Data Wake-up Enable Bit Note:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKRFRTEN : Received Data FIFO Reached Threshold Wake-up Enable Bit Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKRS485EN : RS-485 Address Match (AAD Mode) Wake-up Enable Bit Note1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. Note2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKTOUTEN : Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit Note1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode. Note2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTSWKF : nCTS Wake-up Flag This bit is set if chip wake-up from power-down state by nCTS wake-up. Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATWKF : Incoming Data Wake-up Flag This bit is set if chip wake-up from power-down state by data wake-up. Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RFRTWKF : Received Data FIFO Reached Threshold Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up. Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485WKF : RS-485 Address Match (AAD Mode) Wake-up Flag This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOUTWKF : Received Data FIFO Threshold Time-out Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up. Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STCOMP : Start Bit Compensation Value These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode. Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
bits : 0 - 15 (16 bit)
access : read-write

LINRTOIC : LIN Response Time-out Comparator
bits : 0 - 23 (24 bit)
access : read-write

LINWKC : LIN Send Wake-up Signal Length Counter
bits : 0 - 23 (24 bit)
access : read-write

SENDLINW : LIN Send Wake-up Enable Bit Note1: When this bit is set, the UART will send LIN wake-up automatically. When LIN wake-up transfer operation finished, this bit will be cleared automatically.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINWKEN : LIN Wake-up Enable Bit Note1: When the system is in Power-down mode, LIN wake-up event will wake up system from Power-down mode.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINWKF : LIN Wake-up Flag This bit is set if chip wake-up from power-down state by LIN wake-up. Note1: If LINWKEN (UART_LINWKCTL[28]) is enabled, the LIN wake-up event will cause this bit set to '1'. Note2: This bit can be cleared by writing '1' to it.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXRST : RX Field Software Reset When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXRST : TX Field Software Reset When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RFITL : RX FIFO Interrupt Trigger Level When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled, and an interrupt will be generated).
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOFF : Receiver Disable Bit The receiver is disabled or not (set 1 to disable receiver). Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTSTRGLV : nRTS Trigger Level for Auto-flow Control Note: This field is used for auto nRTS flow control.
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WLS : Word Length Selection This field sets UART word length.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NSB : Number of 'STOP Bit'
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBE : Parity Bit Enable Bit Note: Parity bit is generated on each outgoing character and is checked on each incoming data.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EPE : Even Parity Enable Bit Note: This bit has effect only when PBE (UART_LINE[3]) is set.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPE : Stick Parity Enable Bit Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BCB : Break Control Bit Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PSS : Parity Bit Source Selection The parity bit can be selected to be generated and checked automatically or by software. Note1: This bit has effect only when PBE (UART_LINE[3]) is set. Note2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXDINV : TX Data Inverted Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART, LIN, or RS485 function.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXDINV : RX Data Inverted Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART, LIN, or RS485 function.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.