SYST_CTRL

SYST_LOAD

SYST_VAL

ICSR

VTOR

AIRCR

SCR

CCR

SHPR2

SHPR3

SHCSR

SAU_CTRL

SAU_TYPE

SAU_RNR

SAU_RBAR

SAU_RLAR

ENABLE : System Tick Counter Enabled
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TICKINT : System Tick Interrupt Enabled
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKSRC : System Tick Clock Source Selection
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COUNTFLAG : System Tick Counter Flag Returns 1 if timer counted to 0 since last time this register was read. COUNTFLAG is set by a count transition from 1 to 0. COUNTFLAG is cleared on read or by a write to the Current Value register.
bits : 16 - 16 (1 bit)
access : read-write

RELOAD : System Tick Reload Value Value to load into the Current Value register when the counter reaches 0.
bits : 0 - 23 (24 bit)
access : read-write

CURRENT : System Tick Current Value Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ.
bits : 0 - 23 (24 bit)
access : read-write

VECTACTIVE : Number of the Current Active Exception
bits : 0 - 8 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTPENDING : Number of the Highest Pended Exception
bits : 12 - 20 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRPENDING : Interrupt Pending Flag, Excluding NMI and Faults (Read Only)
bits : 22 - 22 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISRPREEMPT : Interrupt Preempt Bit (Read Only) If set, a pending exception will be serviced on exit from the debug halt state.
bits : 23 - 23 (1 bit)
access : read-only

PENDSTCLR : SysTick Exception Clear-pending Bit Write Operation: Note: This is a write only bit. To clear the PENDST bit, you must 'write 0 to PENDSTSET and write 1 to PENDSTCLR' at the same time.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PENDSTSET : SysTick Exception Set-pending Bit Write Operation:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PENDSVCLR : PendSV Clear-pending Bit Write Operation: Note: This is a write only bit. To clear the PENDSV bit, you must 'write 0 to PENDSVSET and write 1 to PENDSVCLR' at the same time.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PENDSVSET : PendSV Set-pending Bit Write Operation: Note: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NMIPENDCLR : NMI Bit-pending Bit Note: If AIRCR.BFHFNMINS is 0, this bit is RAZ/WI from Non-secure state.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NMIPENDSET : NMI Set-pending Bit Write Operation: Note: If AIRCR.BFHFNMINS is 0, this bit is RAZ/WI from Non-secure state.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TBLOFF : Table Offset Bits The vector table address for the selected Security state.
bits : 9 - 31 (23 bit)
access : read-write

VECTCLRACTIVE : Exception Active Status Clear Bit Setting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions This bit is write only and can only be written when the core is halted. Note: It is the debugger's responsibility to re-initialize the stack.
bits : 1 - 1 (1 bit)
access : read-write

SYSRESETREQ : System Reset Request Bit Writing This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested This bit is write only and self-cleared as part of the reset sequence.
bits : 2 - 2 (1 bit)
access : read-write

SYSRESETREQS : System Reset Request Secure Only Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BFHFNMINS : BusFault, HardFault, AndNMI Non-secure Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRIS : Priority Secure Exceptions Bit
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENDIANNESS : Data Endianness
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTORKEY : Register Access Key When writing this register, this field should be 0x05FA, otherwise the write action will be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.
bits : 16 - 31 (16 bit)
access : read-write

SLEEPONEXIT : Sleep-on-exit Enable Control This bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLEEPDEEP : Processor Deep Sleep and Sleep Mode Selection Control Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLEEPDEEPS : SLEEPDEEP Bit Accessible Selection Control whether the SLEEPDEEP bit is only accessible from the Secure state.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEVONPEND : Send Event on Pending When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UNALIGN_TRP : Unaligned Trap This bit is RAO/WI.
bits : 3 - 3 (1 bit)
access : read-write

DIV_0_TRP : Divide by Zero Trap This bit is RAZ/WI.
bits : 4 - 4 (1 bit)
access : read-write

BFHFNMIGN : BusFault in HardFault or NMI Ignore This bit is RAZ/WI.
bits : 8 - 8 (1 bit)
access : read-write

STKOFHFNMIGN : Stack Overflow in HardFault and NMI Ignore This bit is RAZ/WI.
bits : 10 - 10 (1 bit)
access : read-write

DC : Data Cache Enable Bit This bit is RAZ/WI.
bits : 16 - 16 (1 bit)
access : read-write

IC : Instruction Cache Enable Bit This bit is RAZ/WI.
bits : 17 - 17 (1 bit)
access : read-write

BP : Branch Prediction Enable Bit This bit is RAZ/WI.
bits : 18 - 18 (1 bit)
access : read-write

PRI_11 : Priority of System Handler 11 - SVCall '0' denotes the highest priority and '3' denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI_14 : Priority of System Handler 14 - PendSV '0' denotes the highest priority and '3' denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_15 : Priority of System Handler 15 - SysTick '0' denotes the highest priority and '3' denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

HARDFAULTPENDED : HardFault Exception Pended State This bit indicates and allows modification of the pending state after HardFault exception corresponding to the selected Security state. This bit is banked between Security states. The possible values of this bit are:
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENABLE : SAU Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALLNS : All Non-secure
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SREGION : SAU Regions Indicates the number of regions implemented by the Security Attribution Unit.
bits : 0 - 7 (8 bit)
access : read-only

REGION : Current Region of SAU Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR. Set a value to select the region to be configure through SAU_RBAR and SAU_RLAR. It can be set to 0 ~ the value of SAU_TYPE -1.
bits : 0 - 7 (8 bit)
access : read-write

BADDR : Base Address of Currently Selected Region The base address of the region selected by SAU_RNR. SAU region is 32-byte-aligned.
bits : 5 - 31 (27 bit)
access : read-write

RENABLE : Region Enable Bit Enable or disable the currently selected region set by SAU_RNR.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NSC : Non-secure Callable Setting Bit Controls whether Non-secure state is permitted to execute an SG instruction from this region.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LADDR : Limit Address of Currently Selected Region The limited address of the region selected by SAU_RNR. The region of the selected SAU region is [SAU_RBAR.BADDR,5'b00000] ~ [LADDR,5'b11111]
bits : 5 - 31 (27 bit)
access : read-write