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NVIC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x80 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x100 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x180 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x200 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x280 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x300 Bytes (0x0)
size : 0x74 byte (0x0)
mem_usage : registers
protection :

Registers

NVIC_ISER0 (ISER0)

NVIC_ISPR0 (ISPR0)

NVIC_ISPR1 (ISPR1)

NVIC_ISPR2 (ISPR2)

NVIC_ISPR3 (ISPR3)

NVIC_ICPR0 (ICPR0)

NVIC_ICPR1 (ICPR1)

NVIC_ICPR2 (ICPR2)

NVIC_ICPR3 (ICPR3)

NVIC_IABR0 (IABR0)

NVIC_IABR1 (IABR1)

NVIC_IABR2 (IABR2)

NVIC_IABR3 (IABR3)

NVIC_ITNS0 (ITNS0)

NVIC_ITNS1 (ITNS1)

NVIC_ITNS2 (ITNS2)

NVIC_ITNS3 (ITNS3)

NVIC_IPR0 (IPR0)

NVIC_IPR1 (IPR1)

NVIC_IPR2 (IPR2)

NVIC_IPR3 (IPR3)

NVIC_IPR4 (IPR4)

NVIC_IPR5 (IPR5)

NVIC_IPR6 (IPR6)

NVIC_IPR7 (IPR7)

NVIC_IPR8 (IPR8)

NVIC_IPR9 (IPR9)

NVIC_IPR10 (IPR10)

NVIC_IPR11 (IPR11)

NVIC_IPR12 (IPR12)

NVIC_IPR13 (IPR13)

NVIC_IPR14 (IPR14)

NVIC_IPR15 (IPR15)

NVIC_IPR16 (IPR16)

NVIC_IPR17 (IPR17)

NVIC_IPR18 (IPR18)

NVIC_IPR19 (IPR19)

NVIC_IPR20 (IPR20)

NVIC_IPR21 (IPR21)

NVIC_IPR22 (IPR22)

NVIC_IPR23 (IPR23)

NVIC_IPR24 (IPR24)

NVIC_IPR25 (IPR25)

NVIC_IPR26 (IPR26)

NVIC_IPR27 (IPR27)

NVIC_IPR28 (IPR28)

NVIC_ISER1 (ISER1)

NVIC_ISER2 (ISER2)

NVIC_ICER0 (ICER0)

NVIC_ICER1 (ICER1)

NVIC_ICER2 (ICER2)

NVIC_ICER3 (ICER3)

NVIC_ISER3 (ISER3)


NVIC_ISER0 (ISER0)

IRQ00 ~ IRQ31 Set-enable Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISER0 NVIC_ISER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt Set Enable Bit The NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled. Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt Disabled

1 : 1

Interrupt Enabled

End of enumeration elements list.


NVIC_ISPR0 (ISPR0)

IRQ00 ~ IRQ31 Set-pending Control Register
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISPR0 NVIC_ISPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt Set-pending The NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending. Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt is not pending

1 : 1

Changes interrupt state to pending. Interrupt is pending

End of enumeration elements list.


NVIC_ISPR1 (ISPR1)

IRQ32 ~ IRQ63 Set-pending Control Register
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISPR1 NVIC_ISPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt Set-pending The NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending. Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt is not pending

1 : 1

Changes interrupt state to pending. Interrupt is pending

End of enumeration elements list.


NVIC_ISPR2 (ISPR2)

IRQ64 ~ IRQ95 Set-pending Control Register
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISPR2 NVIC_ISPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt Set-pending The NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending. Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt is not pending

1 : 1

Changes interrupt state to pending. Interrupt is pending

End of enumeration elements list.


NVIC_ISPR3 (ISPR3)

IRQ96 ~ IRQ115 Set-pending Control Register
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISPR3 NVIC_ISPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt Set-pending The NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending. Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt is not pending

1 : 1

Changes interrupt state to pending. Interrupt is pending

End of enumeration elements list.


NVIC_ICPR0 (ICPR0)

IRQ00 ~ IRQ31 Clear-pending Control Register
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICPR0 NVIC_ICPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALPEND

CALPEND : Interrupt Clear-pending The NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending. Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt is not pending

1 : 1

Removes pending state an interrupt. Interrupt is pending

End of enumeration elements list.


NVIC_ICPR1 (ICPR1)

IRQ32 ~ IRQ63 Clear-pending Control Register
address_offset : 0x184 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICPR1 NVIC_ICPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALPEND

CALPEND : Interrupt Clear-pending The NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending. Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt is not pending

1 : 1

Removes pending state an interrupt. Interrupt is pending

End of enumeration elements list.


NVIC_ICPR2 (ICPR2)

IRQ64 ~ IRQ95 Clear-pending Control Register
address_offset : 0x188 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICPR2 NVIC_ICPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALPEND

CALPEND : Interrupt Clear-pending The NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending. Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt is not pending

1 : 1

Remove pending state an interrupt. Interrupt is pending

End of enumeration elements list.


NVIC_ICPR3 (ICPR3)

IRQ96 ~ IRQ115 Clear-pending Control Register
address_offset : 0x18C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICPR3 NVIC_ICPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALPEND

CALPEND : Interrupt Clear-pending The NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending. Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt is not pending

1 : 1

Remove pending state an interrupt. Interrupt is pending

End of enumeration elements list.


NVIC_IABR0 (IABR0)

IRQ00 ~ IRQ31 Active Bit Register
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IABR0 NVIC_IABR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt Active Flags The NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

Interrupt not active

1 : 1

Interrupt active

End of enumeration elements list.


NVIC_IABR1 (IABR1)

IRQ32 ~ IRQ63 Active Bit Register
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IABR1 NVIC_IABR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt Active Flags The NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

interrupt not active

1 : 1

interrupt active

End of enumeration elements list.


NVIC_IABR2 (IABR2)

IRQ64 ~ IRQ95 Active Bit Register
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IABR2 NVIC_IABR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt Active Flags The NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

interrupt not active

1 : 1

interrupt active

End of enumeration elements list.


NVIC_IABR3 (IABR3)

IRQ96 ~ IRQ115 Active Bit Register
address_offset : 0x20C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IABR3 NVIC_IABR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt Active Flags The NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

interrupt not active

1 : 1

interrupt active

End of enumeration elements list.


NVIC_ITNS0 (ITNS0)

IRQ00 ~ IRQ31 Interrupt Target Non-secure Register
address_offset : 0x280 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ITNS0 NVIC_ITNS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITNS

ITNS : Interrupt Target Non-secure Register The NVIC_ITNS0-NVIC_INTS3 registers, determines whether each interrupt targets Non-secure or Secure state. This register is RAZ/WI when accessed as Non-secure.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

Interrupt targets Secure state

1 : 1

Interrupt targets Non-secure state

End of enumeration elements list.


NVIC_ITNS1 (ITNS1)

IRQ32 ~ IRQ63 Interrupt Target Non-secure Register
address_offset : 0x284 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ITNS1 NVIC_ITNS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITNS

ITNS : Interrupt Target Non-secure Register The NVIC_ITNS0-NVIC_INTS3 registers, determines whether each interrupt targets Non-secure or Secure state. Note: This register is RAZ/WI when accessed as Non-secure.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

Interrupt targets Secure state

1 : 1

Interrupt targets Non-secure state

End of enumeration elements list.


NVIC_ITNS2 (ITNS2)

IRQ64 ~ IRQ95 Interrupt Target Non-secure Register
address_offset : 0x288 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ITNS2 NVIC_ITNS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITNS

ITNS : Interrupt Target Non-secure Register The NVIC_ITNS0-NVIC_INTS3 registers, determines whether each interrupt targets Non-secure or Secure state. Note: This register is RAZ/WI when accessed as Non-secure.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

Interrupt targets Secure state

1 : 1

Interrupt targets Non-secure state

End of enumeration elements list.


NVIC_ITNS3 (ITNS3)

IRQ96 ~ IRQ115 Interrupt Target Non-secure Register
address_offset : 0x28C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ITNS3 NVIC_ITNS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITNS

ITNS : Interrupt Target Non-secure Register The NVIC_ITNS0-NVIC_INTS3 registers, determines whether each interrupt targets Non-secure or Secure state. Note: This register is RAZ/WI when accessed as Non-secure.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

Interrupt targets Secure state

1 : 1

Interrupt targets Non-secure state

End of enumeration elements list.


NVIC_IPR0 (IPR0)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x300 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR0 NVIC_IPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_4n_0 PRI_4n_1 PRI_4n_2 PRI_4n_3

PRI_4n_0 : Priority of IRQ_4n+0 '0' denotes the highest priority and '8' denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI_4n_1 : Priority of IRQ_4n+1 '0' denotes the highest priority and '8' denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI_4n_2 : Priority of IRQ_4n+2 '0' denotes the highest priority and '8' denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_4n_3 : Priority of IRQ_4n+3 '0' denotes the highest priority and '8' denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write


NVIC_IPR1 (IPR1)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x304 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR1 NVIC_IPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR2 (IPR2)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x308 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR2 NVIC_IPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR3 (IPR3)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x30C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR3 NVIC_IPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR4 (IPR4)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x310 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR4 NVIC_IPR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR5 (IPR5)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x314 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR5 NVIC_IPR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR6 (IPR6)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x318 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR6 NVIC_IPR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR7 (IPR7)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x31C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR7 NVIC_IPR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR8 (IPR8)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x320 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR8 NVIC_IPR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR9 (IPR9)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x324 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR9 NVIC_IPR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR10 (IPR10)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x328 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR10 NVIC_IPR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR11 (IPR11)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x32C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR11 NVIC_IPR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR12 (IPR12)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x330 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR12 NVIC_IPR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR13 (IPR13)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x334 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR13 NVIC_IPR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR14 (IPR14)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x338 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR14 NVIC_IPR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR15 (IPR15)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x33C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR15 NVIC_IPR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR16 (IPR16)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x340 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR16 NVIC_IPR16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR17 (IPR17)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x344 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR17 NVIC_IPR17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR18 (IPR18)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x348 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR18 NVIC_IPR18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR19 (IPR19)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x34C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR19 NVIC_IPR19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR20 (IPR20)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x350 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR20 NVIC_IPR20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR21 (IPR21)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x354 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR21 NVIC_IPR21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR22 (IPR22)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x358 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR22 NVIC_IPR22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR23 (IPR23)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x35C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR23 NVIC_IPR23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR24 (IPR24)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x360 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR24 NVIC_IPR24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR25 (IPR25)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x364 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR25 NVIC_IPR25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR26 (IPR26)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x368 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR26 NVIC_IPR26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR27 (IPR27)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x36C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR27 NVIC_IPR27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_IPR28 (IPR28)

IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x370 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR28 NVIC_IPR28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NVIC_ISER1 (ISER1)

IRQ32 ~ IRQ63 Set-enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISER1 NVIC_ISER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt Set Enable Bit The NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled. Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt Disabled

1 : 1

Interrupt Enabled

End of enumeration elements list.


NVIC_ISER2 (ISER2)

IRQ64 ~ IRQ95 Set-enable Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISER2 NVIC_ISER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt Set Enable Bit The NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled. Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt Disabled

1 : 1

Interrupt Enabled

End of enumeration elements list.


NVIC_ICER0 (ICER0)

IRQ00 ~ IRQ31 Clear-enable Control Register
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICER0 NVIC_ICER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALENA

CALENA : Interrupt Clear Enable Bit The NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled. Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt Disabled

1 : 1

Interrupt Disabled. Interrupt Enabled

End of enumeration elements list.


NVIC_ICER1 (ICER1)

IRQ32 ~ IRQ63 Clear-enable Control Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICER1 NVIC_ICER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALENA

CALENA : Interrupt Clear Enable Bit The NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled. Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt Disabled

1 : 1

Interrupt Disabled. Interrupt Enabled

End of enumeration elements list.


NVIC_ICER2 (ICER2)

IRQ64 ~ IRQ95 Clear-enable Control Register
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICER2 NVIC_ICER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALENA

CALENA : Interrupt Clear Enable Bit The NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled. Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt Disabled

1 : 1

Interrupt Disabled. Interrupt Enabled

End of enumeration elements list.


NVIC_ICER3 (ICER3)

IRQ96 ~ IRQ115 Clear-enable Control Register
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICER3 NVIC_ICER3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALENA

CALENA : Interrupt Clear Enable Bit The NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled. Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt Disabled

1 : 1

Interrupt Disabled. Interrupt Enabled

End of enumeration elements list.


NVIC_ISER3 (ISER3)

IRQ96 ~ IRQ115 Set-enable Control Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISER3 NVIC_ISER3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt Set Enable Bit The NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled. Write Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt Disabled

1 : 1

Interrupt Enabled

End of enumeration elements list.



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