\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x80 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x100 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x180 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x200 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x280 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x300 Bytes (0x0)
size : 0x74 byte (0x0)
mem_usage : registers
protection :
IRQ00 ~ IRQ31 Set-enable Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Set Enable Bit
The NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled.
Write Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt Disabled
1 : 1
Interrupt Enabled
End of enumeration elements list.
IRQ00 ~ IRQ31 Set-pending Control Register
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt Set-pending
The NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending.
Write Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt is not pending
1 : 1
Changes interrupt state to pending.
Interrupt is pending
End of enumeration elements list.
IRQ32 ~ IRQ63 Set-pending Control Register
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt Set-pending
The NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending.
Write Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt is not pending
1 : 1
Changes interrupt state to pending.
Interrupt is pending
End of enumeration elements list.
IRQ64 ~ IRQ95 Set-pending Control Register
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt Set-pending
The NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending.
Write Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt is not pending
1 : 1
Changes interrupt state to pending.
Interrupt is pending
End of enumeration elements list.
IRQ96 ~ IRQ115 Set-pending Control Register
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt Set-pending
The NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending.
Write Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt is not pending
1 : 1
Changes interrupt state to pending.
Interrupt is pending
End of enumeration elements list.
IRQ00 ~ IRQ31 Clear-pending Control Register
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALPEND : Interrupt Clear-pending
The NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending.
Write Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt is not pending
1 : 1
Removes pending state an interrupt.
Interrupt is pending
End of enumeration elements list.
IRQ32 ~ IRQ63 Clear-pending Control Register
address_offset : 0x184 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALPEND : Interrupt Clear-pending
The NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending.
Write Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt is not pending
1 : 1
Removes pending state an interrupt.
Interrupt is pending
End of enumeration elements list.
IRQ64 ~ IRQ95 Clear-pending Control Register
address_offset : 0x188 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALPEND : Interrupt Clear-pending
The NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending.
Write Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt is not pending
1 : 1
Remove pending state an interrupt.
Interrupt is pending
End of enumeration elements list.
IRQ96 ~ IRQ115 Clear-pending Control Register
address_offset : 0x18C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALPEND : Interrupt Clear-pending
The NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending.
Write Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt is not pending
1 : 1
Remove pending state an interrupt.
Interrupt is pending
End of enumeration elements list.
IRQ00 ~ IRQ31 Active Bit Register
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : Interrupt Active Flags
The NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
Interrupt not active
1 : 1
Interrupt active
End of enumeration elements list.
IRQ32 ~ IRQ63 Active Bit Register
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : Interrupt Active Flags
The NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
interrupt not active
1 : 1
interrupt active
End of enumeration elements list.
IRQ64 ~ IRQ95 Active Bit Register
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : Interrupt Active Flags
The NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
interrupt not active
1 : 1
interrupt active
End of enumeration elements list.
IRQ96 ~ IRQ115 Active Bit Register
address_offset : 0x20C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : Interrupt Active Flags
The NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
interrupt not active
1 : 1
interrupt active
End of enumeration elements list.
IRQ00 ~ IRQ31 Interrupt Target Non-secure Register
address_offset : 0x280 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITNS : Interrupt Target Non-secure Register
The NVIC_ITNS0-NVIC_INTS3 registers, determines whether each interrupt targets Non-secure or Secure state.
This register is RAZ/WI when accessed as Non-secure.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
Interrupt targets Secure state
1 : 1
Interrupt targets Non-secure state
End of enumeration elements list.
IRQ32 ~ IRQ63 Interrupt Target Non-secure Register
address_offset : 0x284 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITNS : Interrupt Target Non-secure Register
The NVIC_ITNS0-NVIC_INTS3 registers, determines whether each interrupt targets Non-secure or Secure state.
Note: This register is RAZ/WI when accessed as Non-secure.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
Interrupt targets Secure state
1 : 1
Interrupt targets Non-secure state
End of enumeration elements list.
IRQ64 ~ IRQ95 Interrupt Target Non-secure Register
address_offset : 0x288 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITNS : Interrupt Target Non-secure Register
The NVIC_ITNS0-NVIC_INTS3 registers, determines whether each interrupt targets Non-secure or Secure state.
Note: This register is RAZ/WI when accessed as Non-secure.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
Interrupt targets Secure state
1 : 1
Interrupt targets Non-secure state
End of enumeration elements list.
IRQ96 ~ IRQ115 Interrupt Target Non-secure Register
address_offset : 0x28C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITNS : Interrupt Target Non-secure Register
The NVIC_ITNS0-NVIC_INTS3 registers, determines whether each interrupt targets Non-secure or Secure state.
Note: This register is RAZ/WI when accessed as Non-secure.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
Interrupt targets Secure state
1 : 1
Interrupt targets Non-secure state
End of enumeration elements list.
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x300 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4n_0 : Priority of IRQ_4n+0
'0' denotes the highest priority and '8' denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write
PRI_4n_1 : Priority of IRQ_4n+1
'0' denotes the highest priority and '8' denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write
PRI_4n_2 : Priority of IRQ_4n+2
'0' denotes the highest priority and '8' denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write
PRI_4n_3 : Priority of IRQ_4n+3
'0' denotes the highest priority and '8' denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x304 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x308 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x30C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x310 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x314 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x318 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x31C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x320 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x324 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x328 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x32C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x330 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x334 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x338 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x33C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x340 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x344 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x348 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x34C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x350 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x354 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x358 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x35C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x360 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x364 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x368 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x36C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ115 Priority Control Register
address_offset : 0x370 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ32 ~ IRQ63 Set-enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Set Enable Bit
The NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled.
Write Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt Disabled
1 : 1
Interrupt Enabled
End of enumeration elements list.
IRQ64 ~ IRQ95 Set-enable Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Set Enable Bit
The NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled.
Write Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt Disabled
1 : 1
Interrupt Enabled
End of enumeration elements list.
IRQ00 ~ IRQ31 Clear-enable Control Register
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALENA : Interrupt Clear Enable Bit
The NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.
Write Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt Disabled
1 : 1
Interrupt Disabled.
Interrupt Enabled
End of enumeration elements list.
IRQ32 ~ IRQ63 Clear-enable Control Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALENA : Interrupt Clear Enable Bit
The NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.
Write Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt Disabled
1 : 1
Interrupt Disabled.
Interrupt Enabled
End of enumeration elements list.
IRQ64 ~ IRQ95 Clear-enable Control Register
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALENA : Interrupt Clear Enable Bit
The NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.
Write Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt Disabled
1 : 1
Interrupt Disabled.
Interrupt Enabled
End of enumeration elements list.
IRQ96 ~ IRQ115 Clear-enable Control Register
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALENA : Interrupt Clear Enable Bit
The NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.
Write Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt Disabled
1 : 1
Interrupt Disabled.
Interrupt Enabled
End of enumeration elements list.
IRQ96 ~ IRQ115 Set-enable Control Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Set Enable Bit
The NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled.
Write Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt Disabled
1 : 1
Interrupt Enabled
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.