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SCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x10 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x50 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x60 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

Registers

DPM_CTL (CTL)

DPM_SPW0 (SPW0)

DPM_SPW1 (SPW1)

DPM_SPW2 (SPW2)

DPM_SPW3 (SPW3)

DPM_STS (STS)

DPM_NSCTL (NSCTL)

DPM_NSSTS (NSSTS)

DPM_NSPW0 (NSPW0)

DPM_NSPW1 (NSPW1)

DPM_NSPW2 (NSPW2)

DPM_NSPW3 (NSPW3)


DPM_CTL (CTL)

Secure DPM Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPM_CTL DPM_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBGDIS LOCK PWCMP PWUPD INTEN DACCWDIS DACCDIS RWVCODE

DBGDIS : Set Secure DPM Debug Disable Bit When this bit is read as 0, it can be written to 1 to configure the Secure DPM DBGDIS bit (DBGDISS). When written: Note: This bit can be set to 1 but cannot be cleared to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No operation

#1 : 1

Trigger the process to set DBGDISS configuration bit

End of enumeration elements list.

LOCK : Set Secure DPM Debug Lock Bit When this bit is read as 0, it can be written to 1 to configure the Secure DPM LOCK bit (LOCKS). When written: Note: This bit can be set to 1 but cannot be cleared to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No operation

#1 : 1

Trigger the process to set LOCKS configuration bit

End of enumeration elements list.

PWCMP : Secure DPM Password Compare Bit Set to enter the process of compare Secure DPM password. Note: This bit will be cleared after the comparison process is finished.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No operation

#1 : 1

Compare Secure DPM password

End of enumeration elements list.

PWUPD : Secure DPM Password Update Bit Set to enter the process of updating Secure DPM password. Note 1: This bit should be set with PWCMP equal to 0. Note 2: This bit will be cleared after the update process is finished.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No operation

#1 : 1

Update Secure DPM password

End of enumeration elements list.

INTEN : DPM Interrupt Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

DPM interrupt function Enabled

#1 : 1

DPM interrupt function Disabled

End of enumeration elements list.

DACCWDIS : Secure DPM Debug Write Access Disable Bit This bit disables the ability of external debugger to set Secure DPM registers for debug authentication.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

External debugger can set Secure DPM registers

#1 : 1

External debugger cannot set Secure DPM registers

End of enumeration elements list.

DACCDIS : Debug Access Disable Bit This bit disables the accessibility of external debugger to all DPM registers.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

External debugger can read/write DPM registers

#1 : 1

External debugger cannot read/write DPM registers

End of enumeration elements list.

RWVCODE : Write Verify Code and Read Verify Code Read operation:
bits : 24 - 31 (8 bit)
access : read-write

Enumeration:

0x5a : 90

The write verify code, 0x5A, is needed to do a valid write to DPM_CTL

0xa5 : 165

The read access for DPM_CTL is correct

End of enumeration elements list.


DPM_SPW0 (SPW0)

Secure DPM Password 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DPM_SPW0 DPM_SPW0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PW

PW : Password Write password[31:0] to this register to update or compare Secure DPM password. It is write-only and always read as 0xFFFFFFFF.
bits : 0 - 31 (32 bit)
access : write-only


DPM_SPW1 (SPW1)

Secure DPM Password 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DPM_SPW1 DPM_SPW1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PW

PW : Password Write password[63:32] to this register to update or compare Secure DPM password. It is write-only and always read as 0xFFFFFFFF.
bits : 0 - 31 (32 bit)
access : write-only


DPM_SPW2 (SPW2)

Secure DPM Password 2
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DPM_SPW2 DPM_SPW2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PW

PW : Password Write password[95:64] to this register to update or compare Secure DPM password. It is write-only and always read as 0xFFFFFFFF.
bits : 0 - 31 (32 bit)
access : write-only


DPM_SPW3 (SPW3)

Secure DPM Password 3
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DPM_SPW3 DPM_SPW3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PW

PW : Password Write password[127:96] to this register to update or compare Secure DPM password. It is write-only and always read as 0xFFFFFFFF.
bits : 0 - 31 (32 bit)
access : write-only


DPM_STS (STS)

Secure DPM Status Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPM_STS DPM_STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY INT PWCERR PWUOK PWFMAX PWUCNT DBGDIS LOCK PWOK

BUSY : DPM Busy Flag (Read Only) This bit indicates the DPM is busy.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

DPM is not busy and writing to any register is accepted

#1 : 1

DPM is busy and other bits in DPM_STS register are not valid and writing to any register is ignored

End of enumeration elements list.

INT : DPM Interrupt Flag (Read Only) This bit indicates the interrupt is triggered. Note: This bit is cleared automatically when PWCERR flag in both DPM_STS and DPM_NSSTS are 0.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt is not enabled or no password comparison flag is set

#1 : 1

Interrupt is enabled and PWCERR flag in either DPM_STS or DPM_NSSTS register is not cleared

End of enumeration elements list.

PWCERR : Secure DPM Password Compared Error Flag This bit indicates the result of Secure DPM password comparison. When read: Note: This flag is write-one-clear.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The result of Secure DPM password is correct

#1 : 1

The result of Secure DPM password is incorrect

End of enumeration elements list.

PWUOK : Secure DPM Password Updated Flag This bit indicates Secure DPM password has been updated successfully. When read: Note: This flag is write-one-clear.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No successful updating process has happened

#1 : 1

There is at least one successful updating process since last clearing of this bit

End of enumeration elements list.

PWFMAX : Secure DPM Password Fail Times Maximum Reached Flag (Read Only) This bit indicates if the fail times of comparing Secure DPM password reached max times.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Max time has not reached and Secure DPM password comparison can be triggered

#1 : 1

Max time reached and Secure DPM password comparison cannot be processed anymore

End of enumeration elements list.

PWUCNT : Secure DPM Password Updated Times (Read Only) This bit indicates how many times of secure password has been updated. The max value is 7. If PWUCNT reached the max value, Secure DPM password cannot be updated anymore.
bits : 8 - 10 (3 bit)
access : read-only

DBGDIS : Secure Debug Disable Flag (Read Only) This bit indicates the current value of DBGDISS bit. {PWOK, LOCK, DBGDIS} bits define the current state of DPM.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#000 : 0

DEFAULT state. LOCKED state

#001 : 1

CLOSE state

#101 : 5

OPEN state

End of enumeration elements list.

LOCK : Secure Debug Lock Flag (Read Only) This bit indicates the current value of LOCKS bit.
bits : 17 - 17 (1 bit)
access : read-only

PWOK : Secure Password OK Flag (Read Only) This bit indicates the Secure DPM password has been checked and is correct.
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

#0 : 0

The Secure DPM password has not been checked pass, yet

#1 : 1

The Secure DPM password has been checked pass since last cold reset

End of enumeration elements list.


DPM_NSCTL (NSCTL)

Non-secure DPM Control Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPM_NSCTL DPM_NSCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBGDIS LOCK PWCMP PWUPD DACCWDIS RWVCODE

DBGDIS : Set Non-secure DPM Debug Disable Bit When this bit is read as 0, it can be written to 1 to configure the Non-secure DPM DBGDIS bit (DBGDISNS). When written: Note: This bit can be set to 1 but cannot be cleared to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No operation

#1 : 1

Trigger the process to set DBGDISNS configuration bit

End of enumeration elements list.

LOCK : Set Non-secure DPM Debug Lock Bit When this bit is read as 0, it can be written to 1 to configure the Non-secure DPM LOCK bit (LOCKNS). When written: Note: This bit can be set to 1 but cannot be cleared to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No operation

#1 : 1

Trigger the process to set LOCKNS configuration bit

End of enumeration elements list.

PWCMP : Non-secure DPM Password Compare Bit Set to enter the process of compare Non-secure DPM password. Note: This bit will be cleared after the comparison process is finished.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No operation

#1 : 1

Compare Non-secure DPM password

End of enumeration elements list.

PWUPD : Non-secure DPM Password Update Bit Set to enter the process of updating Non-secure DPM password. Note 1: This bit should be set with PWCMP equal to 0. Note 2: This bit will be cleared after the update process is finished.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No operation

#1 : 1

Update Non-secure DPM password

End of enumeration elements list.

DACCWDIS : Debug Write Access Disable Bit This bit disables the ability of external debugger to set Non-secure DPM registers for debug authentication.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

External debugger can set Non-secure DPM registers

#1 : 1

External debugger cannot set Non-secure DPM registers

End of enumeration elements list.

RWVCODE : Write Verify Code and Read Verify Code Read operation:
bits : 24 - 31 (8 bit)
access : read-write

Enumeration:

0x5a : 90

The write verify code, 0x5A, is needed to do a valid write to DPM_NSCTL

0xa5 : 165

The read access for DPM_NSCTL is correct

End of enumeration elements list.


DPM_NSSTS (NSSTS)

Non-secure DPM Status Register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPM_NSSTS DPM_NSSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY PWCERR PWUOK PWFMAX PWUCNT DBGDIS LOCK PWOK

BUSY : DPM Busy Flag (Read Only) This bit indicates the DPM is busy.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

DPM is not busy and writing to any register is accepted

#1 : 1

DPM is busy and other bits in DPM_NSSTS register are not valid and writing to any register is ignored

End of enumeration elements list.

PWCERR : Non-secure DPM Password Compared Error Flag This bit indicates the result of Non-secure DPM password comparison. Note: This flag is write-one-clear.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The result of Non-secure DPM password is correct

#1 : 1

The result of Non-secure DPM password is incorrect

End of enumeration elements list.

PWUOK : Non-secure DPM Password Updated Flag This bit indicates Non-secure DPM password has been updated correctly. When read: Note: This flag is write-one-clear.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No successful updating process has happened

#1 : 1

There is at least one successful updating process since last clearing of this bit

End of enumeration elements list.

PWFMAX : Non-secure DPM Password Fail Times Maximum Reached Flag (Read Only) This bit indicates if the fail times of comparing Non-secure DPM password reached max times.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Max time has not reached and Non-secure DPM password comparison can be triggered

#1 : 1

Max time reached and Non-secure DPM password comparison cannot be processed anymore

End of enumeration elements list.

PWUCNT : Non-secure DPM Password Updated Times (Read Only) This bit indicates how many times of non-secure password has been updated. The max value is 7. If PWUCNT reached the max value, Non-secure DPM password cannot be updated anymore.
bits : 8 - 10 (3 bit)
access : read-only

DBGDIS : Non-secure Debug Disable Flag (Read Only) This bit indicates the current value of DBGDISNS bit. {PWOK, LOCK, DBGDIS} bits define the current state of DPM.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#000 : 0

DEFAULT state. LOCKED state

#001 : 1

CLOSE state

#101 : 5

OPEN state

End of enumeration elements list.

LOCK : Non-secure Debug Lock Flag (Read Only) This bit indicates the current value of LOCKNS bit.
bits : 17 - 17 (1 bit)
access : read-only

PWOK : Non-secure Password OK Flag (Read Only) This bit indicates the Non-secure DPM password has been checked and is correct.
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

#0 : 0

The Non-secure DPM password has not been checked pass, yet

#1 : 1

The Non-secure DPM password has been checked pass since last cold reset

End of enumeration elements list.


DPM_NSPW0 (NSPW0)

Non-secure DPM Password 0
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DPM_NSPW0 DPM_NSPW0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PW

PW : Password Write password[31:0] to this register to update or compare Non-secure DPM password. It is write-only and always read as 0xFFFFFFFF.
bits : 0 - 31 (32 bit)
access : write-only


DPM_NSPW1 (NSPW1)

Non-secure DPM Password 1
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DPM_NSPW1 DPM_NSPW1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PW

PW : Password Write password[63:32] to this register to update or compare Non-secure DPM password. It is write-only and always read as 0xFFFFFFFF.
bits : 0 - 31 (32 bit)
access : write-only


DPM_NSPW2 (NSPW2)

Non-secure DPM Password 2
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DPM_NSPW2 DPM_NSPW2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PW

PW : Password Write password[95:64] to this register to update or compare Non-secure DPM password. It is write-only and always read as 0xFFFFFFFF.
bits : 0 - 31 (32 bit)
access : write-only


DPM_NSPW3 (NSPW3)

Non-secure DPM Password 3
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DPM_NSPW3 DPM_NSPW3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PW

PW : Password Write password[127:96] to this register to update or compare Non-secure DPM password. It is write-only and always read as 0xFFFFFFFF.
bits : 0 - 31 (32 bit)
access : write-only



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